VisionSOM-RT-ETH Datasheet and Pinout - Revision history

Piotrzbysinski: /* Pinout */

2025-09-05T11:23:39Z

Pinout

← Older revision		Revision as of 11:23, 5 September 2025
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	Important notes:<br />		Important notes:<br />
	1. LCD_DATAxx pins can be used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <b>Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions.</b> <br />		1. LCD_DATAxx pins can be used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <b>Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions.</b> <br />
	2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 ~~model~~.<br />		2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 MCU.<br />
	3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).		3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).

2025-09-05T11:23:12Z

Pinout

← Older revision		Revision as of 11:23, 5 September 2025
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	== Pinout ==		== Pinout ==
	Important notes:<br />		Important notes:<br />
	1. LCD_DATAxx pins can be ~~internally~~ used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions. <br />		1. LCD_DATAxx pins can be used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <b>Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions.</b> <br />
	2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 model.<br />		2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 model.<br />
	3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).		3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).

2025-09-05T11:22:43Z

Pinout

← Older revision		Revision as of 11:22, 5 September 2025
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	== Pinout ==		== Pinout ==
	Important notes:<br />		Important notes:<br />
	1. LCD_DATAxx pins ~~are~~ internally used for boot sequence configuration. We recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <br />		1. LCD_DATAxx pins can be internally used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions. <br />
	2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 model.<br />		2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 model.<br />
	3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).		3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).

2025-09-05T11:17:59Z

Pinout

← Older revision		Revision as of 11:17, 5 September 2025
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	\| -		\| -
	\| M9		\| M9
	\| Optional external coin battery for SNVS power domain, must be held between 2.9V and 3.3V if the system requires keeping real time and other data on OFF state.<br /> Leave open if not used.<br /> Parallel power supply for SNVS domain.<br /> Connected in parallel with the line VDD-SNVS-3V3.		\| Optional external coin battery for SNVS power domain, must be held between 2.9V and 3.6V if the system requires keeping real time and other data on OFF state.<br /> Leave open if not used.<br /> Parallel power supply for SNVS domain.<br /> Connected in parallel with the line VDD-SNVS-3V3.
	\|- style="vertical-align:bottom;"		\|- style="vertical-align:bottom;"
	\| 9		\| 9

2025-09-05T11:17:27Z

Electrical parameters

← Older revision		Revision as of 11:17, 5 September 2025
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	\| VDD-COIN-3V		\| VDD-COIN-3V
	\| SNVS Backup<br />Battery Supply		\| SNVS Backup<br />Battery Supply
	\| 2.66		\| 2.9
	\| -		\| -
	\| 3.6		\| 3.6

2025-09-05T11:17:01Z

Electrical parameters

← Older revision		Revision as of 11:17, 5 September 2025
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	\|}		\|}
	Notes:<br />		Notes:<br />
	1. Excluding external load connected to +3.3VOUT lines.<br />		1. Excluding external load connected to +3.3VOUT lines and with Ethernet PHY in stand-by mode.<br />
	2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />		2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />

2025-09-05T11:12:48Z

On-board Ethernet PHY configuration

← Older revision		Revision as of 11:12, 5 September 2025
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	2. MDC and MDIO lines are not used for PHY configuration.<br />		2. MDC and MDIO lines are not used for PHY configuration.<br />
	3. Hardware interrupt (line INTRP/NAND_TREE of PHY) is not connected to MCU.<br />		3. Hardware interrupt (line INTRP/NAND_TREE of PHY) is not connected to MCU.<br />
			4. The clock signal for Ethernet PHY (line ENET1.TX-CLK) is generated on GPIO_B1_10 (ball B13) of MCU.<br />

	{\| class="wikitable"		{\| class="wikitable"

2025-09-05T11:08:57Z

On-board JTAG connector

@@ Line 1,533: / Line 1,533: @@
 The VisionSOM-RT-ETH is equipped with on-board JTAG connector.
 [[File:VisionSOM-RT-ETH-JTAG.png|center]]
 == Dimensions ==
 [[File:visionSOM-RT-ETH-size.png|600px|center]]

2025-09-05T11:03:00Z

On-board JTAG connector

← Older revision		Revision as of 11:03, 5 September 2025
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	== On-board JTAG connector ==		== On-board JTAG connector ==
	~~Important notes:<br />~~		The VisionSOM-RT-ETH is equipped with on-board JTAG connector.
	[[File:VisionSOM-RT-ETH-JTAG.png\|center]]		[[File:VisionSOM-RT-ETH-JTAG.png\|center]]

	== Dimensions ==		== Dimensions ==
	[[File:visionSOM-RT-ETH-size.png\|600px\|center]]		[[File:visionSOM-RT-ETH-size.png\|600px\|center]]

2025-09-05T11:02:08Z

On-board JTAG connector

← Older revision		Revision as of 11:02, 5 September 2025
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	== On-board JTAG connector ==		== On-board JTAG connector ==
	Important notes:<br />		Important notes:<br />
			[[File:VisionSOM-RT-ETH-JTAG.png\|center]]

	== Dimensions ==		== Dimensions ==
	[[File:visionSOM-RT-ETH-size.png\|600px\|center]]		[[File:visionSOM-RT-ETH-size.png\|600px\|center]]