Personal tools

VisionSOM-6ULL Datasheet and Pinout: Difference between revisions

From SomLabs Wiki

Jump to: navigation, search
 
 
(65 intermediate revisions by 3 users not shown)
Line 5: Line 5:


The VisionSOM-6ULL family is a SODIMM-sized SoM based on the NXP i.MX6 ULL application processor which features an advanced implementation of a single ARM Cortex-A7 core (at speeds up to 900MHz).
The VisionSOM-6ULL family is a SODIMM-sized SoM based on the NXP i.MX6 ULL application processor which features an advanced implementation of a single ARM Cortex-A7 core (at speeds up to 900MHz).
 
The VisionSOM-6ULL is a low power highly integrated SoM (System on Module) featuring high computation power and 802.11b/g/n Wi-Fi and Bluetooth v4.1 connectivity. The option of integrated, fully certified Wi-Fi and Bluetooth module simplifies the carrier board design and is ideally suited for wireless application. The VisionSOM-6ULL provides a variety memory configuration including flexible range of DDR3L, NAND, eMMC and SD memory card that meets our customers requirements.
The VisionSOM-6ULL is a low power highly integrated SoM (System on Module) featuring high computation power and 802.11b/g/n Wi-Fi and Bluetooth v5.1 connectivity. The option of integrated, fully certified Wi-Fi and Bluetooth module simplifies the carrier board design and is ideally suited for wireless application. The VisionSOM-6ULL provides a variety memory configuration including flexible range of DDR3L, NAND, eMMC and SD memory card that meets our customers requirements.


The SoM supports connections to a variety of interfaces: two high-speed USB on-the-go with PHY, dual Ethernet, audio, display with touch panel and serial interfaces. In addition, the system supports industrial grade targeting embedded application.
The SoM supports connections to a variety of interfaces: two high-speed USB on-the-go with PHY, dual Ethernet, audio, display with touch panel and serial interfaces. In addition, the system supports industrial grade targeting embedded application.
Line 20: Line 20:
* Cash Register
* Cash Register
* 2D barcode scanners and printers
* 2D barcode scanners and printers
* Smart grid Infrastructure
* Smart grid infrastructure
* IoT gateways
* IoT gateways
* Residential getaways
* Residential gateways
* Machine vision equipment
* Machine vision equipment
* Robotics
* Robotics
Line 32: Line 32:
* Up to 512MB SDRAM DDR3L
* Up to 512MB SDRAM DDR3L
* Up to 512MB NAND Flash / 32GB eMMC / uSD memory card
* Up to 512MB NAND Flash / 32GB eMMC / uSD memory card
* Optional Murata 802.11b/g/n Wi-Fi and Bluetooth v4.1+EDR module
* Optional Murata 802.11b/g/n Wi-Fi and Bluetooth v5.2 module
* Power-efficient and cost-optimized solution
* Power-efficient and cost-optimized solution
* Ideal for industrial IoT and embedded applications
* Ideal for industrial IoT and embedded applications
Line 139: Line 139:
                     {"value" : "256N", "description" : "256MB NAND"},
                     {"value" : "256N", "description" : "256MB NAND"},
                     {"value" : "512N", "description" : "512MB NAND"},
                     {"value" : "512N", "description" : "512MB NAND"},
                     {"value" : "04GE", "description" : "4Gb eMMC"},
                     {"value" : "04GE", "description" : "4GB eMMC"},
                     {"value" : "08GE", "description" : "8Gb eMMC"},
                     {"value" : "08GE", "description" : "8GB eMMC"},
                     {"value" : "16GE", "description" : "16Gb eMMC"},
                     {"value" : "16GE", "description" : "16GB eMMC"},
                     {"value" : "32GE", "description" : "32Gb eMMC"}
                     {"value" : "32GE", "description" : "32GB eMMC"}
                 ]
                 ]
     },
     },
Line 155: Line 155:
       "values" : [
       "values" : [
                     {"value" : "0SF", "description" : "No Special Features"},
                     {"value" : "0SF", "description" : "No Special Features"},
                     {"value" : "1WB", "description" : "Built-in 802.11b/g/n Wi-Fi and Bluetooth v4.1+EDR Module"}
                     {"value" : "1WB", "description" : "Built-in 802.11b/g/n Wi-Fi and Bluetooth v5.1 Module"}
                 ]
                 ]
     },
     },
Line 168: Line 168:
       "values" : [
       "values" : [
                     {"value" : "C", "description" : "Consumer: 0 to +70 C "},
                     {"value" : "C", "description" : "Consumer: 0 to +70 C "},
                     {"value" : "SI", "description" : "Industrial with Wi-Fi: -30 to +70 C"},
                     {"value" : "E", "description" : "Extended with Wi-Fi: -25 to +70 C"},
                     {"value" : "I", "description" : "Industrial: -40 to +85 C"}
                     {"value" : "I", "description" : "Industrial: -40 to +85 C"}
                 ]
                 ]
Line 181: Line 181:
       "symbol" : "V",
       "symbol" : "V",
       "values" : [
       "values" : [
                     {"value" : "A", "description" : "Version 1.0"}
                     {"value" : "A", "description" : "Version 1.0"},
                    {"value" : "B", "description" : "Version 1.1"}
                 ]
                 ]
     }
     }
Line 188: Line 189:
   ]
   ]
__orderingInfoEnd__
__orderingInfoEnd__


== Block Diagram ==
== Block Diagram ==
[[File:Som-block-ULL.png|center]]
[[File:VisionSOM-6ULL-block_diagram.png|center]]


== Operating ranges ==
== Operating ranges ==
Line 215: Line 215:
| Industrial range w/o WiFi module
| Industrial range w/o WiFi module
|-
|-
| <center>-30…+70</center>
| <center>-25…+70</center>
| Industrial range with WiFi module
| Industrial range with WiFi module
|-
|-
Line 242: Line 242:
| V
| V
|-
|-
| +5VIN
| Total Supply Current<sup>1</sup>
| -
| -
| Total Supply Current<sup>1</sup>
| 115
| x
| 155
| x
| mA
| x
| A
|-
|-
| VGPIO
| VGPIO
Line 288: Line 288:
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />


== SODIMM pinout ==
== SOM pinout (v1.1 and v1.2) ==
{| class="wikitable sortable"
Important notes <br />
! SODIMM<br>PIN
1. Detail pin configurations description you can find, edit and arrange in dedicated MEX files (with free "i.MX Pin Tool" configurational tool):
! Functional<br />
[https://somlabs.com/wp-content/uploads/SoMLabs-VisionSoM-6ULL-NAND-SD-eMMC-noWIFI.zip VisionSOM-6ULL without WiFi module and no SDIO1 on edge connector] or
[https://somlabs.com/wp-content/uploads/SoMLabs-VisionSoM-6ULL-NAND-SD-eMMC-noWIFI-extSDIO1.zip VisionSOM-6ULL without WiFi module and with SDIO1 on edge connector] or
[https://somlabs.com/wp-content/uploads/SoMLabs-VisionSoM-6ULL-NAND-SD-eMMC-WiFi.zip VisionSOM-6ULL witht WiFi module on-board]. <br />
2. In module version v1.1 the LCD-DATAxx pins are internally used for boot sequence configuration. We recommend to use LCD-DATAxx lines as outputs or using eFuse boot configuration. <br />
3. In module version v1.2 equipped with NAND Flash the LCD-DATAxx pins are internally used for boot sequence configuration (like in v1.1). We recommend to use LCD-DATAxx lines as outputs or using eFuse boot configuration. <br />
4. In module version v1.2 equipped with eMMC the boot sequence configuration is stored in eFuse (OTP memory in MPU). All LCD-DATAxx pins can be used freely like all others GPIOs. <br />
 
{| class="wikitable"
! style="text-align: center; font-weight: bold;" | SODIMM PIN
! style="text-align: center; font-weight: bold;" | Functional
domain
domain
! Function<br />
! style="text-align: center; font-weight: bold;" | Function name
name
! style="text-align: center; font-weight: bold;" | i.MX6 UltraLite/
! i.MX6 UltraLite/ULL <br />
ULL Pad Name
Pad Name
! style="text-align: center; font-weight: bold;" | Alternate functions
! Alternate <br />
! Description (refer to i.MX6 UltraLite/ULL manuals for details)
functions
! Description <br />
(refer to i.MX6 UltraLite/ULL manuals for details)
|-
|-
| 1
| 1
Line 342: Line 348:
| VDD_SNVS_IN
| VDD_SNVS_IN
| -
| -
| SNVS backup power supply must be held between 2.9V and 3.3V <br />if the system requires keeping real time and other data on OFF state. <br />Internally connected to +3.3V, leave open.
| SNVS backup power supply must be held between 2.9V and 3.3V if the system requires keeping real time and other data on OFF state. Internally connected to +3.3V, leave open.
|-
|-
| 7
| 7
Line 349: Line 355:
| BOOT_MODE1
| BOOT_MODE1
| GPIO5_IO11
| GPIO5_IO11
| BOOT-MODE1 BOOT-MODE0<br />
| BOOT-MODE1 BOOT-MODE0
00 boot from fuses (default)<br />
 
01 serial downloader<br />
00 boot from fuses (default)
10 internal boot<br />
 
01 serial downloader
 
10 internal boot
 
11 reserved
11 reserved
|-
|-
| 8
| 8
Line 360: Line 371:
| VDD_SNVS_IN
| VDD_SNVS_IN
| -
| -
| Optional external coin battery for SNVS power domain, <br />must be held between 2.9V and 3.3V if the system requires <br />keeping real time and other data on OFF state.<br />
| Optional external coin battery for SNVS power domain, must be held between 2.9V and 3.3V if the system requires keeping real time and other data on OFF state.
Leave open if not used.
Leave open if not used.
|-
|-
Line 368: Line 379:
| BOOT_MODE0
| BOOT_MODE0
| GPIO5_IO10
| GPIO5_IO10
| BOOT-MODE1 BOOT-MODE0<br />
| BOOT-MODE1 BOOT-MODE0
00 boot from fuses (default)<br />
 
01 serial downloader<br />
00 boot from fuses (default)
10 internal boot<br />
 
01 serial downloader
 
10 internal boot
 
11 reserved
11 reserved
|-
|-
| 10
| 10
Line 386: Line 402:
| USB_OTG2_VBUS
| USB_OTG2_VBUS
| -
| -
| +5V USB bus. <br />Leave open if not used.
| +5V USB bus. Leave open if not used.
|-
|-
| 12
| 12
Line 400: Line 416:
| USB_OTG1_VBUS
| USB_OTG1_VBUS
| -
| -
| +5V USB bus. <br />Leave open if not used.
| +5V USB bus. Leave open if not used.
|-
|-
| 14
| 14
Line 407: Line 423:
| SRC_RESET_B
| SRC_RESET_B
|  
|  
| Input for power interrupt generation. <br />Leave open if not used.
| Input for power interrupt generation. Leave open if not used.
|-
|-
| 15
| 15
Line 421: Line 437:
| POR_B
| POR_B
| -
| -
| Cold reset negative logic input resets all modules and logic in the IC.<br />
| Cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on <br />reset signal (logical AND, both internal and external <br />signals are considered active low).
May be used in addition to internally generated power on reset signal (logical AND, both internal and external signals are considered active low).
|-
|-
| 17
| 17
Line 541: Line 557:
| JTAG_MOD
| JTAG_MOD
| -
| -
| Default: JTAG MOD input or universal GPIO with 3.3V logic levels. Leave open if not used.
| Leave open if not used.
|-
|-
| 34
| 34
Line 569: Line 585:
| CCM_CLK1_N
| CCM_CLK1_N
| -
| -
| General purpose differential high speed clock input/output.<br />
| General purpose differential high speed clock input/output.
Leave open if not used.
Leave open if not used.
|-
|-
Line 584: Line 600:
| CCM_CLK1_P
| CCM_CLK1_P
| -
| -
| General purpose differential high speed clock input/output.<br />
| General purpose differential high speed clock input/output.
Leave open if not used.
Leave open if not used.
|-
|-
Line 613: Line 629:
| JTAG_TDI
| JTAG_TDI
| -
| -
| Default: JTAG TDI input or universal GPIO with 3.3V logic levels.
| JTAG TDI input line or GPIO.
|-
|-
| 44
| 44
Line 626: Line 642:
| GPIO-8
| GPIO-8
| GPIO1_IO08
| GPIO1_IO08
| PWM1_OUT<br />
| PWM1_OUT
WDOG1_WDOG_B<br />
 
SPDIF_OUT<br />
WDOG1_WDOG_B
CSI_VSYNC<br />
 
USDHC2_VSELECT<br />
SPDIF_OUT
CCM_PMIC_RDY<br />
 
CSI_VSYNC
 
USDHC2_VSELECT
 
CCM_PMIC_RDY
 
UART5_RTS_B
UART5_RTS_B
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 640: Line 663:
| JTAG_TMS
| JTAG_TMS
| -
| -
| Default: JTAG TMS output or universal GPIO with 3.3V logic levels.
| JTAG TMS input line or GPIO.
|-
|-
| 47
| 47
Line 646: Line 669:
| GPIO-4
| GPIO-4
| GPIO1_IO04
| GPIO1_IO04
| ENET1_REF_CLK1<br />
| ENET1_REF_CLK1
PWM3_OUT<br />
 
USB_OTG1_PWR<br />
PWM3_OUT
USDHC1_RESET_B<br />
 
ENET2_1588_EVENT0_IN<br />
USB_OTG1_PWR
 
USDHC1_RESET_B
 
ENET2_1588_EVENT0_IN
 
UART5_TX
UART5_TX
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 659: Line 688:
| JTAG_TRST_B
| JTAG_TRST_B
| -
| -
| JTAG TRST input line (active L).
| JTAG TRST input line (active L) or GPIO.
|-
|-
| 49
| 49
Line 665: Line 694:
| GPIO-5
| GPIO-5
| GPIO1_IO05
| GPIO1_IO05
| ENET2_REF_CLK2<br />
| ENET2_REF_CLK2
PWM4_OUT<br />
 
ANATOP_OTG2_ID<br />
PWM4_OUT
CSI_FIELD<br />
 
USDHC1_VSELECT<br />
ANATOP_OTG2_ID
ENET2_1588_EVENT0_OUT<br />
 
CSI_FIELD
 
USDHC1_VSELECT
 
ENET2_1588_EVENT0_OUT
 
UART5_RX
UART5_RX
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
WLAN-ENABLE in SOM with WiFi/BT module
|-
|-
| 50
| 50
Line 693: Line 730:
| JTAG_TDO
| JTAG_TDO
| -
| -
| Default: JTAG TDO output or universal GPIO with 3.3V logic levels.
| JTAG TDO output line or GPIO.
|-
|-
| 53
| 53
Line 699: Line 736:
| GPIO-7
| GPIO-7
| GPIO1_IO07
| GPIO1_IO07
| NET1_MDC<br />
| ENET1_MDC
ENET2_MDC<br />
 
USB_OTG_HOST_MODE<br />
ENET2_MDC
CSI_PIXCLK<br />
 
USDHC2_CD_B<br />
USB_OTG_HOST_MODE
CCM_STOP<br />
 
CSI_PIXCLK
 
USDHC2_CD_BCCM_STOP
 
UART1_RTS_B
UART1_RTS_B
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 713: Line 755:
| JTAG_TCK
| JTAG_TCK
| -
| -
| Default: JTAG TCK input or universal GPIO with 3.3V logic levels.
| JTAG TCK input line or GPIO.
Connected to JTAG-TCK line (via separating resistor 10k).
|-
|-
| 55
| 55
Line 719: Line 762:
| GPIO-3
| GPIO-3
| GPIO1_IO03
| GPIO1_IO03
| I2C1_SDA<br />
| I2C1_SDA
GPT1_COMPARE3<br />
 
USB_OTG2_OC<br />
GPT1_COMPARE3
USDHC1_CD_B<br />
 
CCM_DI0_EXT_CLK<br />
USB_OTG2_OC
 
USDHC1_CD_B
 
CCM_DI0_EXT_CLK
 
SRC_TESTER_ACK
SRC_TESTER_ACK
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 731: Line 780:
| GPIO-9
| GPIO-9
| GPIO1_IO09
| GPIO1_IO09
| PWM2_OUT<br />
| PWM2_OUT
WDOG1_WDOG_ANY<br />
 
SPDIF_IN<br />
WDOG1_WDOG_ANY
CSI_HSYNC<br />
 
USDHC2_RESET_B<br />
SPDIF_IN
USDHC1_RESET_B<br />
 
UART5_CTS_B
CSI_HSYNC
 
USDHC2_RESET_B
 
USDHC1_RESET_B
 
UART5_CTS_B
 
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 744: Line 800:
| UART1-TXD
| UART1-TXD
| UART1_TX_DATA
| UART1_TX_DATA
| ENET1_RDATA02<br />
| ENET1_RDATA02
I2C3_SCL<br />
 
CSI_DATA02<br />
I2C3_SCL
GPT1_COMPARE1<br />
 
GPIO1_IO16<br />
CSI_DATA02
SPDIF_OUT<br />
 
UART5_TX of
GPT1_COMPARE1
| Default: UART1 TxD output<br />
 
or universal GPIO with 3.3V logic levels.
GPIO1_IO16
 
SPDIF_OUT
 
UART5_TX
 
| Default: UART1 TxD output or universal GPIO with 3.3V logic levels.
|-
|-
| 58
| 58
Line 758: Line 820:
| GPIO-2
| GPIO-2
| GPIO1_IO02
| GPIO1_IO02
| I2C1_SCL<br />
| I2C1_SCL
GPT1_COMPARE2<br />
 
USB_OTG2_PWR<br />
GPT1_COMPARE2
ENET1_REF_CLK_25M<br />
 
USDHC1_WP<br />
USB_OTG2_PWR
SDMA_EXT_EVENT00<br />
 
SRC_ANY_PU_RESET<br />
ENET1_REF_CLK_25M
 
USDHC1_WPS
 
DMA_EXT_EVENT00
 
SRC_ANY_PU_RESET
 
UART1_TX
UART1_TX
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 786: Line 856:
| GPIO-6
| GPIO-6
| GPIO1_IO06
| GPIO1_IO06
| ENET1_MDIO<br />
| ENET1_MDIO
ENET2_MDIO<br />
 
USB_OTG_PWR_WAKE<br />
ENET2_MDIO
CSI_MCLK<br />
 
USDHC2_WP<br />
USB_OTG_PWR_WAKE
CCM_WAIT<br />
 
CCM_REF_EN_B<br />
CSI_MCLK
 
USDHC2_WPCCM_WAIT
 
CCM_REF_EN_B
 
UART1_CTS_B
UART1_CTS_B
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 800: Line 876:
| GPIO-1
| GPIO-1
| GPIO1_IO01
| GPIO1_IO01
| I2C2_SDA<br />
| I2C2_SDA
GPT1_COMPARE1<br />
 
USB_OTG1_OC<br />
GPT1_COMPARE1
ENET2_REF_CLK2<br />
 
MQS_LEFT<br />
USB_OTG1_OC
ENET1_1588_EVENT0_OUT<br />
 
SRC_EARLY_RESET<br />
ENET2_REF_CLK2
 
MQS_LEFT
 
ENET1_1588_EVENT0_OUT
 
SRC_EARLY_RESET
 
WDOG1_WDOG_B
WDOG1_WDOG_B
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 814: Line 898:
| UART1-RXD
| UART1-RXD
| UART1_RX_DATA
| UART1_RX_DATA
| ENET1_RDATA03<br />
| ENET1_RDATA03
I2C3_SDA<br />
 
CSI_DATA03<br />
I2C3_SDA
GPT1_CLK<br />
 
GPIO1_IO17<br />
CSI_DATA03
SPDIF_IN<br />
 
GPT1_CLK
 
GPIO1_IO17
 
SPDIF_IN
 
UART5_RX
UART5_RX
| Default: UART1 RxD input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART1 RxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 64
| 64
Line 828: Line 918:
| GPIO-0
| GPIO-0
| GPIO1_IO00
| GPIO1_IO00
| I2C2_SCL<br />
| I2C2_SCL
GPT1_CAPTURE1<br />
 
ANATOP_OTG1_ID<br />
GPT1_CAPTURE1
ENET1_REF_CLK1<br />
 
MQS_RIGHT<br />
ANATOP_OTG1_ID
ENET1_1588_EVENT0_IN<br />
 
SRC_SYSTEM_RESET<br />
ENET1_REF_CLK1
 
MQS_RIGHT
 
ENET1_1588_EVENT0_IN
 
SRC_SYSTEM_RESET
 
WDOG3_WDOG_B
WDOG3_WDOG_B
| Universal GPIO with 3.3V logic levels.
| Universal GPIO with 3.3V logic levels.
|-
|-
Line 842: Line 940:
| UART2-TXD
| UART2-TXD
| UART2_TX_DATA
| UART2_TX_DATA
| ENET1_TDATA02<br />
| ENET1_TDATA02
I2C4_SCL<br />
 
CSI_DATA06<br />
I2C4_SCL
GPT1_CAPTURE1<br />
 
GPIO1_IO20<br />
CSI_DATA06
 
GPT1_CAPTURE1
 
GPIO1_IO20
 
ECSPI3_SS0
ECSPI3_SS0
| Default: UART2 TxD output<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART2 TxD output or universal GPIO with 3.3V logic levels.
|-
|-
| 66
| 66
Line 855: Line 958:
| UART1-CTS
| UART1-CTS
| UART1_CTS_B
| UART1_CTS_B
| ENET1_RX_CLK<br />
| ENET1_RX_CLK
USDHC1_WP<br />
 
CSI_DATA04<br />
USDHC1_WP
ENET2_1588_EVENT1_IN<br />
 
GPIO1_IO18<br />
CSI_DATA04
USDHC2_WP<br />
 
ENET2_1588_EVENT1_IN
 
GPIO1_IO18
 
USDHC2_WP
 
UART5_CTS_B
UART5_CTS_B
| Default: UART1 CTS output<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART1 CTS output or universal GPIO with 3.3V logic levels.
|-
|-
| 67
| 67
Line 869: Line 978:
| UART2-RXD
| UART2-RXD
| UART2_RX_DATA
| UART2_RX_DATA
| ENET1_TDATA03<br />
| ENET1_TDATA03
I2C4_SDA<br />
 
CSI_DATA07<br />
I2C4_SDA
GPT1_CAPTURE2<br />
 
GPIO1_IO21<br />
CSI_DATA07
SJC_DONE<br />
 
GPT1_CAPTURE2
 
GPIO1_IO21
 
SJC_DONE
 
ECSPI3_SCLK
ECSPI3_SCLK
| Default: UART2 RxD input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART2 RxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 68
| 68
Line 883: Line 998:
| UART5-RXD
| UART5-RXD
| UART5_RX_DATA
| UART5_RX_DATA
| ENET2_COL<br />
| ENET2_COL
I2C2_SDA<br />
 
CSI_DATA15<br />
I2C2_SDA
CSU_CSU_INT_DEB<br />
 
GPIO1_IO31<br />
CSI_DATA15
ECSPI2_MISO<br />
 
CSU_CSU_INT_DEB
 
GPIO1_IO31
 
ECSPI2_MISO
 
EPDC_PWRCTRL03
EPDC_PWRCTRL03
| Default: UART5 RxD input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART5 RxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 69
| 69
Line 897: Line 1,018:
| UART3-TXD
| UART3-TXD
| UART3_TX_DATA
| UART3_TX_DATA
| ENET2_RDATA02<br />
| ENET2_RDATA02
CSI_DATA01<br />
 
UART2_CTS_B<br />
CSI_DATA01
GPIO1_IO24<br />
 
UART2_CTS_B
 
GPIO1_IO24
 
SJC_JTAG_ACT
SJC_JTAG_ACT
| Default: UART3 TxD input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART3 TxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 70
| 70
Line 923: Line 1,048:
| UART2-CTS
| UART2-CTS
| UART2_CTS_B
| UART2_CTS_B
| ENET1_CRS<br />
| ENET1_CRS
FLEXCAN2_TX<br />
 
CSI_DATA08<br />
FLEXCAN2_TXCSI_DATA08
GPT1_COMPARE2<br />
 
GPIO1_IO22<br />
GPT1_COMPARE2
SJC_DE_B<br />
 
ECSPI3_MOSI
GPIO1_IO22
| Default: UART2 CTS output<br />
 
or universal GPIO with 3.3V logic levels.
SJC_DE_B
 
ECSPI3_MOSI
 
| Default: UART2 CTS output or universal GPIO with 3.3V logic levels.
|-
|-
| 73
| 73
Line 937: Line 1,066:
| UART3-RXD
| UART3-RXD
| UART3_RX_DATA
| UART3_RX_DATA
| ENET2_RDATA03<br />
| ENET2_RDATA03
CSI_DATA00<br />
 
UART2_RTS_B<br />
CSI_DATA00
GPIO1_IO25<br />
 
UART2_RTS_B
 
GPIO1_IO25
 
EPIT1_OUT
EPIT1_OUT
| Default: UART3 RxD input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART3 RxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 74
| 74
Line 949: Line 1,082:
| UART1-RTS
| UART1-RTS
| UART1_RTS_B
| UART1_RTS_B
| ENET1_TX_ER<br />
| ENET1_TX_ER
USDHC1_CD_B<br />
 
CSI_DATA05<br />
USDHC1_CD_BCSI_DATA05
ENET2_1588_EVENT1_OUT<br />
 
GPIO1_IO19<br />
ENET2_1588_EVENT1_OUT
USDHC2_CD_B<br />
 
GPIO1_IO19
 
USDHC2_CD_B
 
UART5_RTS_B
UART5_RTS_B
| Default: UART1 RTS input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART1 RTS input or universal GPIO with 3.3V logic levels.
|-
|-
| 75
| 75
Line 963: Line 1,100:
| UART4-TXD
| UART4-TXD
| UART4_TX_DATA
| UART4_TX_DATA
| ENET2_TDATA02<br />
| ENET2_TDATA02
I2C1_SCL<br />
 
CSI_DATA12<br />
I2C1_SCL
CSU_CSU_ALARM_AUT02<br />
 
GPIO1_IO28<br />
CSI_DATA12
 
CSU_CSU_ALARM_AUT02
 
GPIO1_IO28
 
ECSPI2_SCLK
ECSPI2_SCLK
| Default: UART4 TxD output<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART4 TxD output or universal GPIO with 3.3V logic levels.
|-
|-
| 76
| 76
Line 976: Line 1,118:
| UART3-CTS
| UART3-CTS
| UART3_CTS_B
| UART3_CTS_B
| ENET2_RX_CLK<br />
| ENET2_RX_CLK
FLEXCAN1_TX<br />
 
CSI_DATA10<br />
FLEXCAN1_TX
ENET1_1588_EVENT1_IN<br />
 
GPIO1_IO26<br />
CSI_DATA10
 
ENET1_1588_EVENT1_IN
 
GPIO1_IO26
 
EPIT2_OUT
EPIT2_OUT
| Default: UART3 CTS output<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART3 CTS output or universal GPIO with 3.3V logic levels.
|-
|-
| 77
| 77
Line 989: Line 1,136:
| UART4-RXD
| UART4-RXD
| UART4_RX_DATA
| UART4_RX_DATA
| ENET2_TDATA03<br />
| ENET2_TDATA03
I2C1_SDA<br />
 
CSI_DATA13<br />
I2C1_SDA
CSU_CSU_ALARM_AUT01<br />
 
GPIO1_IO29<br />
CSI_DATA13
ECSPI2_SS0<br />
 
EPDC_PWRCTRL01
CSU_CSU_ALARM_AUT01
| Default: UART4 RxD input<br />
 
or universal GPIO with 3.3V logic levels.
GPIO1_IO29
 
ECSPI2_SS0
 
EPDC_PWRCTRL01
 
| Default: UART4 RxD input or universal GPIO with 3.3V logic levels.
|-
|-
| 78
| 78
Line 1,003: Line 1,156:
| UART2-RTS
| UART2-RTS
| UART2_RTS_B
| UART2_RTS_B
| ENET1_COL<br />
| ENET1_COL
FLEXCAN2_RX<br />
 
CSI_DATA09<br />
FLEXCAN2_RX
GPT1_COMPARE3<br />
 
GPIO1_IO23<br />
CSI_DATA09
SJC_FAIL<br />
 
GPT1_COMPARE3
 
GPIO1_IO23
 
SJC_FAIL
 
ECSPI3_MISO
ECSPI3_MISO
| Default: UART2 RTS input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART2 RTS input or universal GPIO with 3.3V logic levels.
|-
|-
| 79
| 79
Line 1,017: Line 1,176:
| UART5-TXD
| UART5-TXD
| UART5_TX_DATA
| UART5_TX_DATA
| GPIO1_IO30<br />
| GPIO1_IO30
ECSPI2_MOSI<br />
 
EPDC_PWRCTRL02<br />
ECSPI2_MOSI
ENET2_CRS<br />
 
I2C2_SCL<br />
EPDC_PWRCTRL02
CSI_DATA14<br />
 
ENET2_CRS
 
I2C2_SCL
 
CSI_DATA14
 
CSU_CSU_ALARM_AUT00
CSU_CSU_ALARM_AUT00
| Default: UART5 TxD output<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART5 TxD output or universal GPIO with 3.3V logic levels.
|-
|-
| 80
| 80
Line 1,031: Line 1,196:
| UART3-RTS
| UART3-RTS
| UART3_RTS_B
| UART3_RTS_B
| ENET2_TX_ER<br />
| ENET2_TX_ER
FLEXCAN1_RX<br />
 
CSI_DATA11<br />
FLEXCAN1_RX
ENET1_1588_EVENT1_OUT<br />
 
GPIO1_IO27<br />
CSI_DATA11
 
ENET1_1588_EVENT1_OUT
 
GPIO1_IO27
 
WDOG1_WDOG_B
WDOG1_WDOG_B
| Default: UART3 RTS input<br />
 
or universal GPIO with 3.3V logic levels.
| Default: UART3 RTS input or universal GPIO with 3.3V logic levels.
|-
|-
| 81
| 81
Line 1,156: Line 1,326:
| ENET1-RXD0
| ENET1-RXD0
| ENET1_RX_DATA0
| ENET1_RX_DATA0
| UART4_RTS_B<br />
| UART4_RTS_B
PWM1_OUT<br />
 
CSI_DATA16<br />
PWM1_OUT
FLEXCAN1_TX<br />
 
GPIO2_IO00<br />
CSI_DATA16
KPP_ROW00<br />
 
USDHC1_LCTL<br />
FLEXCAN1_TX
EPDC_SDCE04
 
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
GPIO2_IO00
 
KPP_ROW00
 
USDHC1_LCTL
 
EPDC_SDCE04
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 98
| 98
Line 1,177: Line 1,355:
| ENET1-RXD1
| ENET1-RXD1
| ENET1_RX_DATA1
| ENET1_RX_DATA1
| UART4_CTS_B<br />
| UART4_CTS_B
PWM2_OUT<br />
 
CSI_DATA17<br />
PWM2_OUT
FLEXCAN1_RX<br />
 
GPIO2_IO01<br />
CSI_DATA17
KPP_COL00<br />
 
USDHC2_LCTL<br />
FLEXCAN1_RX
 
GPIO2_IO01
 
KPP_COL00
 
USDHC2_LCTL
 
EPDC_SDCE05
EPDC_SDCE05
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 100
| 100
Line 1,198: Line 1,384:
| ENET1-CRS-DV
| ENET1-CRS-DV
| ENET1_RX_EN
| ENET1_RX_EN
| UART5_RTS_B<br />
| UART5_RTS_B
CSI_DATA18<br />
 
FLEXCAN2_TX<br />
CSI_DATA18
GPIO2_IO02<br />
 
KPP_ROW01<br />
FLEXCAN2_TX
USDHC1_VSELECT<br />
 
GPIO2_IO02
 
KPP_ROW01
 
USDHC1_VSELECT
 
EPDC_SDCE06
EPDC_SDCE06
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 102
| 102
| Power
| Power
| +5VIN
| +5VIN
| -
|  
| -
|  
| +4.0-5.5V input power supply.
| +4.0-5.5V input power supply.
|-
|-
Line 1,224: Line 1,417:
| Power
| Power
| +5VIN
| +5VIN
| -
|  
| -
|  
| +4.0-5.5V input power supply.
| +4.0-5.5V input power supply.
|-
|-
Line 1,232: Line 1,425:
| ENET2-TX-CLK
| ENET2-TX-CLK
| ENET2_TX_CLK
| ENET2_TX_CLK
| UART8_CTS_B<br />
| UART8_CTS_B
ECSPI4_MISO<br />
 
ENET2_REF_CLK2<br />
ECSPI4_MISO
GPIO2_IO14<br />
 
KPP_ROW07<br />
ENET2_REF_CLK2
ANATOP_OTG2_ID<br />
 
GPIO2_IO14
 
KPP_ROW07
 
ANATOP_OTG2_ID
 
EPDC_SDDO14
EPDC_SDDO14
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
10R resistor connected in series.
|-
|-
| 106
| 106
| Power
| Power
| +5VIN
| +5VIN
| -
|  
| -
|  
| +4.0-5.5V input power supply.
| +4.0-5.5V input power supply.
|-
|-
Line 1,258: Line 1,459:
| Power
| Power
| +5VIN
| +5VIN
| -
|  
| -
|  
| +4.0-5.5V input power supply.
| +4.0-5.5V input power supply.
|-
|-
Line 1,266: Line 1,467:
| ENET2-RXER
| ENET2-RXER
| ENET2_RX_ER
| ENET2_RX_ER
| UART8_RTS_B<br />
| UART8_RTS_B
ECSPI4_SS0<br />
 
EIM_ADDR25<br />
ECSPI4_SS0
GPIO2_IO15<br />
 
KPP_COL07<br />
EIM_ADDR25
WDOG1_WDOG_ANY<br />
 
GPIO2_IO15
 
KPP_COL07
 
WDOG1_WDOG_ANY
 
EPDC_SDDO15
EPDC_SDDO15
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
Connected to WDOG-B line.
|-
|-
| 110
| 110
Line 1,286: Line 1,495:
| ENET2-RXD0
| ENET2-RXD0
| ENET2_RX_DATA0
| ENET2_RX_DATA0
| UART6_TX<br />
| UART6_TX
I2C3_SCL<br />
 
ENET1_MDIO<br />
I2C3_SCL
GPIO2_IO08<br />
 
KPP_ROW04<br />
ENET1_MDIO
USB_OTG1_PWR<br />
 
GPIO2_IO08
 
KPP_ROW04
 
USB_OTG1_PWR
 
EPDC_SDDO08
EPDC_SDDO08
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 112
| 112
Line 1,306: Line 1,522:
| ENET2-RXD1
| ENET2-RXD1
| ENET2_RX_DATA1
| ENET2_RX_DATA1
| UART6_RX<br />
| UART6_RX
I2C3_SDA<br />
 
ENET1_MDC<br />
I2C3_SDA
GPIO2_IO09<br />
 
KPP_COL04<br />
ENET1_MDC
USB_OTG1_OC<br />
 
EPDC_SDDO09
GPIO2_IO09
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
KPP_COL04
 
USB_OTG1_OCE
 
PDC_SDDO09
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 114
| 114
Line 1,319: Line 1,542:
| ENET1-TXEN
| ENET1-TXEN
| ENET1_TX_EN
| ENET1_TX_EN
| UART6_RTS_B<br />
| UART6_RTS_B
PWM6_OUT<br />
 
CSI_DATA21<br />
PWM6_OUT
ENET2_MDC<br />
 
GPIO2_IO05<br />
CSI_DATA21
KPP_COL02<br />
 
WDOG2_WDOG_RST_B_DEB<br />
ENET2_MDC
 
GPIO2_IO05
 
KPP_COL02
 
WDOG2_WDOG_RST_B_DEB
 
EPDC_SDCE09
EPDC_SDCE09
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 115
| 115
Line 1,347: Line 1,578:
| ENET2-CRS-DV
| ENET2-CRS-DV
| ENET2_RX_EN
| ENET2_RX_EN
| UART7_TX<br />
| UART7_TX
I2C4_SCL<br />
 
EIM_ADDR26<br />
I2C4_SCL
GPIO2_IO10<br />
 
KPP_ROW05<br />
EIM_ADDR26
ENET1_REF_CLK_25M<br />
 
GPIO2_IO10
 
KPP_ROW05
 
ENET1_REF_CLK_25M
 
EPDC_SDDO10
EPDC_SDDO10
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 118
| 118
Line 1,360: Line 1,598:
| ENET1-TX-CLK
| ENET1-TX-CLK
| ENET1_TX_CLK
| ENET1_TX_CLK
| UART7_CTS_B<br />
| UART7_CTS_B
PWM7_OUT<br />
 
CSI_DATA22<br />
PWM7_OUT
ENET1_REF_CLK1<br />
 
GPIO2_IO06<br />
CSI_DATA22
KPP_ROW03<br />
 
GPT1_CLK<br />
ENET1_REF_CLK1
 
GPIO2_IO06
 
KPP_ROW03
 
GPT1_CLK
 
EPDC_SDOED
EPDC_SDOED
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
10R resistor connected in series.
|-
|-
| 119
| 119
Line 1,374: Line 1,621:
| ENET2-TXD1
| ENET2-TXD1
| ENET2_TX_DATA1
| ENET2_TX_DATA1
| UART8_TX<br />
| UART8_TX
ECSPI4_SCLK<br />
 
EIM_EB_B03<br />
ECSPI4_SCLK
GPIO2_IO12<br />
 
KPP_ROW06<br />
EIM_EB_B03
USB_OTG2_PWR<br />
 
GPIO2_IO12
 
KPP_ROW06
 
USB_OTG2_PWR
 
EPDC_SDDO12
EPDC_SDDO12
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 120
| 120
Line 1,394: Line 1,648:
| ENET2-TXEN
| ENET2-TXEN
| ENET2_TX_EN
| ENET2_TX_EN
| UART8_RX<br />
| UART8_RX
ECSPI4_MOSI<br />
 
EIM_ACLK_FREERUN<br />
ECSPI4_MOSI
GPIO2_IO13<br />
 
KPP_COL06<br />
EIM_ACLK_FREERUN
USB_OTG2_OC<br />
 
GPIO2_IO13
 
KPP_COL06
 
USB_OTG2_OC
 
EPDC_SDDO13
EPDC_SDDO13
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
|  
|-
|-
| 122
| 122
Line 1,407: Line 1,668:
| ENET1-TXD0
| ENET1-TXD0
| ENET1_TX_DATA0
| ENET1_TX_DATA0
| UART5_CTS_B<br />
| UART5_CTS_B
CSI_DATA19<br />
 
FLEXCAN2_RX<br />
CSI_DATA19
GPIO2_IO03<br />
 
KPP_COL01<br />
FLEXCAN2_RX
USDHC2_VSELECT<br />
 
GPIO2_IO03
 
KPP_COL01
 
USDHC2_VSELECT
 
EPDC_SDCE07
EPDC_SDCE07
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 123
| 123
Line 1,420: Line 1,688:
| ENET2-TXD0
| ENET2-TXD0
| ENET2_TX_DATA0
| ENET2_TX_DATA0
| UART7_RX<br />
| UART7_RX
I2C4_SDA<br />
 
EIM_EB_B02<br />
I2C4_SDA
GPIO2_IO11<br />
 
KPP_COL05<br />
EIM_EB_B02
 
GPIO2_IO11
 
KPP_COL05
 
EPDC_SDDO11
EPDC_SDDO11
| Ethernet MAC2-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 124
| 124
Line 1,432: Line 1,706:
| ENET1-TXD1
| ENET1-TXD1
| ENET1_TX_DATA1
| ENET1_TX_DATA1
| UART6_CTS_B<br />
| UART6_CTS_B
PWM5_OUT<br />
 
CSI_DATA20<br />
PWM5_OUT
ENET2_MDIO<br />
 
GPIO2_IO04<br />
CSI_DATA20
KPP_ROW02<br />
 
WDOG1_WDOG_RST_B_DEB<br />
ENET2_MDIO
 
GPIO2_IO04
 
KPP_ROW02
 
WDOG1_WDOG_RST_B_DEB
 
EPDC_SDCE08
EPDC_SDCE08
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 125
| 125
Line 1,453: Line 1,735:
| ENET1-RXER
| ENET1-RXER
| ENET1_RX_ER
| ENET1_RX_ER
| UART7_RTS_B<br />
| UART7_RTS_B
PWM8_OUT<br />
 
CSI_DATA23<br />
PWM8_OUT
EIM_CRE<br />
 
GPIO2_IO07<br />
CSI_DATA23
KPP_COL03<br />
 
GPT1_CAPTURE2<br />
EIM_CRE
 
GPIO2_IO07
 
KPP_COL03
 
GPT1_CAPTURE2
 
EPDC_SDOEZ
EPDC_SDOEZ
| Ethernet MAC1-PHY interface signal <br />or universal GPIO with 3.3V logic levels.
 
| Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
|-
|-
| 127
| 127
Line 1,481: Line 1,771:
| LCD-DATA21
| LCD-DATA21
| LCD_DATA21
| LCD_DATA21
| UART8_RX<br />
| UART8_RX
ECSPI1_SS0<br />
 
CSI_DATA13<br />
ECSPI1_SS0
EIM_DATA13<br />
 
GPIO3_IO26<br />
CSI_DATA13
SRC_BT_CFG29<br />
 
USDHC2_DATA1<br />
EIM_DATA13
 
GPIO3_IO26
 
SRC_BT_CFG29
 
USDHC2_DATA1
 
EPDC_SDCE01
EPDC_SDCE01
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 130
| 130
Line 1,502: Line 1,801:
| LCD-DATA22
| LCD-DATA22
| LCD_DATA22
| LCD_DATA22
| MQS_RIGHT<br />
| MQS_RIGHT
ECSPI1_MOSI<br />
 
CSI_DATA14<br />
ECSPI1_MOSI
EIM_DATA14<br />
 
GPIO3_IO27<br />
CSI_DATA14
SRC_BT_CFG30<br />
 
USDHC2_DATA2<br />
EIM_DATA14
USDHC2_DATA2
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
GPIO3_IO27
 
SRC_BT_CFG30
 
USDHC2_DATA2
 
USDHC2_DATA2
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 132
| 132
Line 1,523: Line 1,831:
| LCD-DATA17
| LCD-DATA17
| LCD_DATA17
| LCD_DATA17
| UART7_RX<br />
| UART7_RX
CSI_DATA00<br />
 
EIM_DATA09<br />
CSI_DATA00
GPIO3_IO22<br />
 
SRC_BT_CFG25<br />
EIM_DATA09
USDHC2_DATA7<br />
 
GPIO3_IO22
 
SRC_BT_CFG25
 
USDHC2_DATA7
 
EPDC_GDSP
EPDC_GDSP
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 134
| 134
Line 1,536: Line 1,852:
| LCD-DATA23
| LCD-DATA23
| LCD_DATA23
| LCD_DATA23
| MQS_LEFT<br />
| MQS_LEFT
ECSPI1_MISO<br />
 
CSI_DATA15<br />
ECSPI1_MISO
EIM_DATA15<br />
 
GPIO3_IO28<br />
CSI_DATA15
SRC_BT_CFG31<br />
 
USDHC2_DATA3<br />
EIM_DATA15
 
GPIO3_IO28
 
SRC_BT_CFG31
 
USDHC2_DATA3
 
EPDC_SDCE03
EPDC_SDCE03
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 135
| 135
Line 1,564: Line 1,889:
| LCD-DATA18
| LCD-DATA18
| LCD_DATA18
| LCD_DATA18
| PWM5_OUT<br />
| PWM5_OUT
CA7_MX6ULL_EVENTO<br />
 
CSI_DATA10<br />
CA7_MX6ULL_EVENTO
EIM_DATA10<br />
 
GPIO3_IO23<br />
CSI_DATA10
SRC_BT_CFG26<br />
 
USDHC2_CMD<br />
EIM_DATA10
 
GPIO3_IO23
 
SRC_BT_CFG26
 
USDHC2_CMD
 
EPDC_BDR01
EPDC_BDR01
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 138
| 138
Line 1,578: Line 1,912:
| LCD-DATA19
| LCD-DATA19
| LCD_DATA19
| LCD_DATA19
| PWM6_OUT<br />
| PWM6_OUT
WDOG1_WDOG_ANY<br />
 
CSI_DATA11<br />
WDOG1_WDOG_ANY
EIM_DATA11<br />
 
GPIO3_IO24<br />
CSI_DATA11
SRC_BT_CFG27<br />
 
USDHC2_CLK<br />
EIM_DATA11
 
GPIO3_IO24
 
SRC_BT_CFG27
 
USDHC2_CLK
 
EPDC_VCOM00
EPDC_VCOM00
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 139
| 139
Line 1,592: Line 1,935:
| LCD-DATA13
| LCD-DATA13
| LCD_DATA13
| LCD_DATA13
| SAI3_TX_BCLK<br />
| SAI3_TX_BCLK
CSI_DATA21<br />
 
EIM_DATA05<br />
CSI_DATA21
GPIO3_IO18<br />
 
SRC_BT_CFG13<br />
EIM_DATA05
USDHC2_RESET_B<br />
 
GPIO3_IO18
 
SRC_BT_CFG13
 
USDHC2_RESET_B
 
EPDC_BDR00
EPDC_BDR00
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 140
| 140
Line 1,605: Line 1,956:
| LCD-DATA20
| LCD-DATA20
| LCD_DATA20
| LCD_DATA20
| UART8_TX<br />
| UART8_TX
ECSPI1_SCLK<br />
 
CSI_DATA12<br />
ECSPI1_SCLK
EIM_DATA12<br />
 
GPIO3_IO25<br />
CSI_DATA12
SRC_BT_CFG28<br />
 
USDHC2_DATA0<br />
EIM_DATA12
 
GPIO3_IO25
 
SRC_BT_CFG28
 
USDHC2_DATA0
 
EPDC_VCOM01
EPDC_VCOM01
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 141
| 141
Line 1,619: Line 1,979:
| LCD-DATA14
| LCD-DATA14
| LCD_DATA14
| LCD_DATA14
| SAI3_RX_DATA<br />
| SAI3_RX_DATA
CSI_DATA22<br />
 
EIM_DATA06<br />
CSI_DATA22
GPIO3_IO19<br />
 
SRC_BT_CFG14<br />
EIM_DATA06
USDHC2_DATA4<br />
 
GPIO3_IO19
 
SRC_BT_CFG14
 
USDHC2_DATA4
 
EPDC_SDSHR
EPDC_SDSHR
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 142
| 142
Line 1,632: Line 2,000:
| LCD-DATA15
| LCD-DATA15
| LCD_DATA15
| LCD_DATA15
| SAI3_TX_DATA<br />
| SAI3_TX_DATA
CSI_DATA23<br />
 
EIM_DATA07<br />
CSI_DATA23
GPIO3_IO20<br />
 
SRC_BT_CFG15<br />
EIM_DATA07
USDHC2_DATA5<br />
 
GPIO3_IO20
 
SRC_BT_CFG15
 
USDHC2_DATA5
 
EPDC_GDRL
EPDC_GDRL
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 143
| 143
Line 1,645: Line 2,021:
| LCD-DATA8
| LCD-DATA8
| LCD_DATA08
| LCD_DATA08
| SPDIF_IN<br />
| SPDIF_IN
CSI_DATA16<br />
 
EIM_DATA00<br />
CSI_DATA16
GPIO3_IO13<br />
 
SRC_BT_CFG08<br />
EIM_DATA00
FLEXCAN1_TX<br />
 
GPIO3_IO13
 
SRC_BT_CFG08
 
FLEXCAN1_TX
 
EPDC_PWRIRQ
EPDC_PWRIRQ
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 144
| 144
Line 1,658: Line 2,042:
| LCD-DATA16
| LCD-DATA16
| LCD_DATA16
| LCD_DATA16
| UART7_TX<br />
| UART7_TX
CSI_DATA01<br />
 
EIM_DATA08<br />
CSI_DATA01
GPIO3_IO21<br />
 
SRC_BT_CFG24<br />
EIM_DATA08
USDHC2_DATA6<br />
 
GPIO3_IO21
 
SRC_BT_CFG24
 
USDHC2_DATA6
 
EPDC_GDCLK
EPDC_GDCLK
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 145
| 145
Line 1,671: Line 2,063:
| LCD-DATA9
| LCD-DATA9
| LCD_DATA09
| LCD_DATA09
| SAI3_MCLK<br />
| SAI3_MCLK
CSI_DATA17<br />
 
EIM_DATA01<br />
CSI_DATA17
GPIO3_IO14<br />
 
SRC_BT_CFG09<br />
EIM_DATA01
FLEXCAN1_RX<br />
 
GPIO3_IO14
 
SRC_BT_CFG09
 
FLEXCAN1_RX
 
EPDC_PWRWAKE
EPDC_PWRWAKE
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 146
| 146
Line 1,698: Line 2,098:
| LCD-DATA11
| LCD-DATA11
| LCD_DATA11
| LCD_DATA11
| SAI3_RX_BCLK<br />
| SAI3_RX_BCLK
CSI_DATA19<br />
 
EIM_DATA03<br />
CSI_DATA19
GPIO3_IO16<br />
 
SRC_BT_CFG11<br />
EIM_DATA03
FLEXCAN2_RX<br />
 
GPIO3_IO16
 
SRC_BT_CFG11
 
FLEXCAN2_RX
 
EPDC_PWRSTAT
EPDC_PWRSTAT
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 149
| 149
Line 1,711: Line 2,119:
| LCD-DATA5
| LCD-DATA5
| LCD_DATA05
| LCD_DATA05
| UART8_RTS_B<br />
| UART8_RTS_B
ENET2_1588_EVENT2_OUT<br />
 
SPDIF_OUT<br />
ENET2_1588_EVENT2_OUT
GPIO3_IO10<br />
 
SRC_BT_CFG05<br />
SPDIF_OUT
ECSPI1_SS1<br />
 
GPIO3_IO10
 
SRC_BT_CFG05
 
ECSPI1_SS1
 
EPDC_SDDO05
EPDC_SDDO05
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 150
| 150
Line 1,724: Line 2,140:
| LCD-DATA12
| LCD-DATA12
| LCD_DATA12
| LCD_DATA12
| SAI3_TX_SYNC<br />
| SAI3_TX_SYNC
CSI_DATA20<br />
 
EIM_DATA04<br />
CSI_DATA20
GPIO3_IO17<br />
 
SRC_BT_CFG12<br />
EIM_DATA04
ECSPI1_RDY<br />
 
GPIO3_IO17
 
SRC_BT_CFG12
 
ECSPI1_RDY
 
EPDC_PWRCTRL00
EPDC_PWRCTRL00
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 151
| 151
Line 1,737: Line 2,161:
| LCD-DATA6
| LCD-DATA6
| LCD_DATA06
| LCD_DATA06
| UART7_CTS_B<br />
| UART7_CTS_B
ENET2_1588_EVENT3_IN<br />
 
SPDIF_LOCK<br />
ENET2_1588_EVENT3_IN
GPIO3_IO11<br />
 
SRC_BT_CFG06<br />
SPDIF_LOCK
ECSPI1_SS2<br />
 
GPIO3_IO11
 
SRC_BT_CFG06
 
ECSPI1_SS2
 
EPDC_SDDO06
EPDC_SDDO06
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 152
| 152
Line 1,750: Line 2,182:
| LCD-DATA10
| LCD-DATA10
| LCD_DATA10
| LCD_DATA10
| SAI3_RX_SYNC<br />
| SAI3_RX_SYNC
CSI_DATA18<br />
 
EIM_DATA02<br />
CSI_DATA18
GPIO3_IO15<br />
 
SRC_BT_CFG10<br />
EIM_DATA02
FLEXCAN2_TX<br />
 
EPDC_PWRCOM
GPIO3_IO15
 
SRC_BT_CFG10
 
FLEXCAN2_TX
 
EPDC_PWRCOM
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 153
| 153
Line 1,763: Line 2,203:
| LCD-DATA0
| LCD-DATA0
| LCD_DATA00
| LCD_DATA00
| PWM1_OUT<br />
| PWM1_OUT
ENET1_1588_EVENT2_IN<br />
 
I2C3_SDA<br />
ENET1_1588_EVENT2_IN
GPIO3_IO05<br />
 
SRC_BT_CFG00<br />
I2C3_SDA
SAI1_MCLK<br />
 
GPIO3_IO05
 
SRC_BT_CFG00
 
SAI1_MCLK
 
EPDC_SDDO00
EPDC_SDDO00
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 154
| 154
Line 1,776: Line 2,224:
| LCD-DATA3
| LCD-DATA3
| LCD_DATA03
| LCD_DATA03
| PWM4_OUT<br />
| PWM4_OUT
ENET1_1588_EVENT3_OUT<br />
 
I2C4_SCL<br />
ENET1_1588_EVENT3_OUT
GPIO3_IO08<br />
 
SRC_BT_CFG03<br />
I2C4_SCL
SAI1_RX_DATA<br />
 
EPDC_SDDO03 of
GPIO3_IO08
 
SRC_BT_CFG03
 
SAI1_RX_DATA
 
EPDC_SDDO03
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 155
| 155
Line 1,789: Line 2,245:
| LCD-DATA1
| LCD-DATA1
| LCD_DATA01
| LCD_DATA01
| PWM2_OUT<br />
| PWM2_OUT
ENET1_1588_EVENT2_OUT<br />
 
I2C3_SCL<br />
ENET1_1588_EVENT2_OUT
GPIO3_IO06<br />
 
SRC_BT_CFG01<br />
I2C3_SCL
SAI1_TX_SYNC<br />
 
GPIO3_IO06
 
SRC_BT_CFG01
 
SAI1_TX_SYNC
 
EPDC_SDDO01
EPDC_SDDO01
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 156
| 156
Line 1,809: Line 2,273:
| LCD-RESET
| LCD-RESET
| LCD_RESET
| LCD_RESET
| LCDIF_CS<br />
| LCDIF_CS
CA7_MX6ULL_EVENTI<br />
 
SAI3_TX_DATA<br />
CA7_MX6ULL_EVENT
WDOG1_WDOG_ANY<br />
 
GPIO3_IO04<br />
ISAI3_TX_DATA
ECSPI2_SS3<br />
 
EPDC_GDOE
WDOG1_WDOG_ANY
 
GPIO3_IO04
 
ECSPI2_SS3
 
EPDC_GDOE
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
|-
|-
Line 1,822: Line 2,293:
| LCD-DATA4
| LCD-DATA4
| LCD_DATA04
| LCD_DATA04
| UART8_CTS_B<br />
| UART8_CTS_B
ENET2_1588_EVENT2_IN<br />
 
SPDIF_SR_CLK<br />
ENET2_1588_EVENT2_IN
GPIO3_IO09<br />
 
SRC_BT_CFG04<br />
SPDIF_SR_CLK
SAI1_TX_DATA<br />
 
GPIO3_IO09
 
SRC_BT_CFG04
 
SAI1_TX_DATA
 
EPDC_SDDO04
EPDC_SDDO04
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 159
| 159
Line 1,842: Line 2,321:
| LCD-HSYNC
| LCD-HSYNC
| LCD_HSYNC
| LCD_HSYNC
| LCDIF_RS<br />
| LCDIF_RS
UART4_CTS_B<br />
 
SAI3_TX_BCLK<br />
UART4_CTS_B
WDOG3_WDOG_RST_B_DEB<br />
 
GPIO3_IO02<br />
SAI3_TX_BCLK
ECSPI2_SS1<br />
 
WDOG3_WDOG_RST_B_DEB
 
GPIO3_IO02
 
ECSPI2_SS1
 
EPDC_SDOE
EPDC_SDOE
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
|-
|-
Line 1,855: Line 2,341:
| LCD-CLK
| LCD-CLK
| LCD_CLK
| LCD_CLK
| LCDIF_WR_RWN<br />
| LCDIF_WR_RWN
UART4_TX<br />
 
SAI3_MCLK<br />
UART4_TX
EIM_CS2_B<br />
 
GPIO3_IO00<br />
SAI3_MCLK
WDOG1_WDOG_RST_B_DEB<br />
 
EIM_CS2_B
 
GPIO3_IO00
 
WDOG1_WDOG_RST_B_DEB
 
EPDC_SDCLK
EPDC_SDCLK
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
10R resistor connected in series.
|-
|-
| 162
| 162
Line 1,868: Line 2,362:
| LCD-VSYNC
| LCD-VSYNC
| LCD_VSYNC
| LCD_VSYNC
| LCDIF_BUSY<br />
| LCDIF_BUSY
UART4_RTS_B<br />
 
SAI3_RX_DATA<br />
UART4_RTS_B
WDOG2_WDOG_B<br />
 
GPIO3_IO03<br />
SAI3_RX_DATA
ECSPI2_SS2<br />
 
EPDC_SDCE00
WDOG2_WDOG_B
 
GPIO3_IO03
 
ECSPI2_SS2
 
EPDC_SDCE00
 
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
|-
|-
Line 1,881: Line 2,382:
| LCD-ENABLE
| LCD-ENABLE
| LCD_ENABLE
| LCD_ENABLE
| LCDIF_RD_E<br />
| LCDIF_RD_E
UART4_RX<br />
 
SAI3_TX_SYNC<br />
UART4_RX
EIM_CS3_B<br />
 
GPIO3_IO01<br />
SAI3_TX_SYNC
ECSPI2_RDY<br />
 
EIM_CS3_B
 
GPIO3_IO01
 
ECSPI2_RDY
 
EPDC_SDLE
EPDC_SDLE
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
|-
|-
Line 1,894: Line 2,402:
| LCD-DATA2
| LCD-DATA2
| LCD_DATA02
| LCD_DATA02
| PWM3_OUT<br />
| PWM3_OUT
ENET1_1588_EVENT3_IN<br />
 
I2C4_SDA<br />
ENET1_1588_EVENT3_IN
GPIO3_IO07<br />
 
SRC_BT_CFG02<br />
I2C4_SDA
SAI1_TX_BCLK<br />
 
GPIO3_IO07
 
SRC_BT_CFG02
 
SAI1_TX_BCLK
 
EPDC_SDDO02
EPDC_SDDO02
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 165
| 165
Line 1,914: Line 2,430:
| LCD-DATA7
| LCD-DATA7
| LCD_DATA07
| LCD_DATA07
| UART7_RTS_B<br />
| UART7_RTS_B
ENET2_1588_EVENT3_OUT<br />
 
SPDIF_EXT_CLK<br />
ENET2_1588_EVENT3_OUT
GPIO3_IO12<br />
 
SRC_BT_CFG07<br />
SPDIF_EXT_CLK
ECSPI1_SS3<br />
 
GPIO3_IO12
 
SRC_BT_CFG07
 
ECSPI1_SS3
 
EPDC_SDDO07
EPDC_SDDO07
| LCD interface signal or universal GPIO with 3.3V logic levels.
| LCD interface signal or universal GPIO with 3.3V logic levels.
Internally used as boot configuration input (Notes 2, 3 & 4).
|-
|-
| 167
| 167
Line 1,927: Line 2,451:
| SDIO1-D0
| SDIO1-D0
| SD1_DATA0
| SD1_DATA0
| GPT2_COMPARE3<br />
| GPT2_COMPARE3
SAI2_TX_SYNC<br />
 
FLEXCAN1_TX<br />
SAI2_TX_SYNC
EIM_ADDR21<br />
 
GPIO2_IO18<br />
FLEXCAN1_TX
ANATOP_OTG1_ID
 
EIM_ADDR21
 
GPIO2_IO18
 
ANATOP_OTG1_ID
 
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
Built-in internal pull-up 10k.
|-
|-
| 168
| 168
Line 1,946: Line 2,481:
| SDIO1-D3
| SDIO1-D3
| SD1_DATA3
| SD1_DATA3
| GPT2_CAPTURE2<br />
| GPT2_CAPTURE2
SAI2_TX_DATA<br />
 
FLEXCAN2_RX<br />
SAI2_TX_DATA
EIM_ADDR24<br />
 
GPIO2_IO21<br />
FLEXCAN2_RX
CCM_CLKO2<br />
 
EIM_ADDR24
 
GPIO2_IO21
 
CCM_CLKO2
 
ANATOP_OTG2_ID
ANATOP_OTG2_ID
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
Built-in internal pull-up 10k.
|-
|-
| 170
| 170
Line 1,966: Line 2,514:
| SDIO1-D1
| SDIO1-D1
| SD1_DATA1
| SD1_DATA1
| GPT2_CLK<br />
| GPT2_CLK
SAI2_TX_BCLK<br />
 
FLEXCAN1_RX<br />
SAI2_TX_BCLK
EIM_ADDR22<br />
 
GPIO2_IO19<br />
FLEXCAN1_RX
 
EIM_ADDR22
 
GPIO2_IO19
 
USB_OTG2_PWR
USB_OTG2_PWR
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
Built-in internal pull-up 10k.
|-
|-
| 172
| 172
Line 1,985: Line 2,545:
| SDIO1-CMD
| SDIO1-CMD
| SD1_CMD
| SD1_CMD
| GPT2_COMPARE1<br />
| GPT2_COMPARE1
SAI2_RX_SYNC<br />
 
SPDIF_OUT<br />
SAI2_RX_SYNC
EIM_ADDR19<br />
 
GPIO2_IO16<br />
SPDIF_OUT
SDMA_EXT_EVENT00<br />
 
EIM_ADDR19
 
GPIO2_IO16
 
SDMA_EXT_EVENT00
 
USB_OTG1_PWR
USB_OTG1_PWR
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
Built-in internal pull-up 10k.
|-
|-
| 174
| 174
Line 2,005: Line 2,578:
| SDIO1-D2
| SDIO1-D2
| SD1_DATA2
| SD1_DATA2
| GPT2_CAPTURE1<br />
| GPT2_CAPTURE1
SAI2_RX_DATA<br />
 
FLEXCAN2_TX<br />
SAI2_RX_DATA
EIM_ADDR23<br />
 
GPIO2_IO20<br />
FLEXCAN2_TX
CCM_CLKO1<br />
 
EIM_ADDR23
 
GPIO2_IO20
 
CCM_CLKO1
 
USB_OTG2_OC
USB_OTG2_OC
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
Built-in internal pull-up 10k.
|-
|-
| 176
| 176
Line 2,039: Line 2,625:
| SDIO1-CLK
| SDIO1-CLK
| SD1_CLK
| SD1_CLK
| GPT2_COMPARE2<br />
| GPT2_COMPARE2
SAI2_MCLK<br />
 
SPDIF_IN<br />
SAI2_MCLK
EIM_ADDR20<br />
 
GPIO2_IO17<br />
SPDIF_IN
 
EIM_ADDR20
 
GPIO2_IO17
 
USB_OTG1_OC
USB_OTG1_OC
| SDIO interface signal or universal GPIO with 3.3V logic levels.
| SDIO interface signal or universal GPIO with 3.3V logic levels.
Used by WiFi/BT module if built-in SOM.
|-
|-
| 180
| 180
Line 2,072: Line 2,665:
| CSI-PIXCLK
| CSI-PIXCLK
| CSI_PIXCLK
| CSI_PIXCLK
| USDHC2_WP<br />
| USDHC2_WP
RAWNAND_CE3_B<br />
 
I2C1_SCL<br />
RAWNAND_CE3_B
EIM_OE<br />
 
GPIO4_IO18<br />
I2C1_SCL
SNVS_HP_VIO_5<br />
 
UART6_RX<br />
EIM_OE
ESAI_TX2_RX3
 
GPIO4_IO18
 
SNVS_HP_VIO_5
 
UART6_RX
 
ESAI_TX2_RX3
 
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-WAKE in SOM with WiFi/BT module
|-
|-
| 184
| 184
Line 2,100: Line 2,702:
| CSI-DATA6
| CSI-DATA6
| CSI_DATA06
| CSI_DATA06
| USDHC2_DATA6<br />
| USDHC2_DATA6
ECSPI1_MOSI<br />
 
EIM_AD06<br />
ECSPI1_MOSI
GPIO4_IO27<br />
 
SAI1_RX_DATA<br />
EIM_AD06
USDHC1_RESET_B<br />
 
ESAI_TX5_RX0
GPIO4_IO27
 
SAI1_RX_DATA
 
USDHC1_RESET_BE
 
SAI_TX5_RX0
 
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-PCM-OUT in SOM with WiFi/BT module
|-
|-
| 187
| 187
Line 2,113: Line 2,723:
| CSI-MCLK
| CSI-MCLK
| CSI_MCLK
| CSI_MCLK
| USDHC2_CD_B<br />
| USDHC2_CD_B
RAWNAND_CE2_B<br />
 
I2C1_SDA<br />
RAWNAND_CE2_B
EIM_CS0_B<br />
 
GPIO4_IO17<br />
I2C1_SDA
SNVS_HP_VIO_5_CTL<br />
 
UART6_TX<br />
EIM_CS0_B
 
GPIO4_IO17
 
SNVS_HP_VIO_5_CTL
 
UART6_TX
 
ESAI_TX3_RX2
ESAI_TX3_RX2
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-ENABLE in SOM with WiFi/BT module
|-
|-
| 188
| 188
Line 2,127: Line 2,746:
| CSI-DATA7
| CSI-DATA7
| CSI_DATA07
| CSI_DATA07
| USDHC2_DATA7<br />
| USDHC2_DATA7
ECSPI1_MISO<br />
 
EIM_AD07<br />
ECSPI1_MISO
GPIO4_IO28<br />
 
SAI1_TX_DATA<br />
EIM_AD07
USDHC1_VSELECT<br />
 
GPIO4_IO28
 
SAI1_TX_DATA
 
USDHC1_VSELECT
 
ESAI_TX0
ESAI_TX0
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-PCM-IN in SOM with WiFi/BT module
|-
|-
| 189
| 189
Line 2,147: Line 2,774:
| CSI-DATA5
| CSI-DATA5
| CSI_DATA05
| CSI_DATA05
| USDHC2_DATA5<br />
| USDHC2_DATA5
USDHC2_DATA5<br />
 
EIM_AD05<br />
USDHC2_DATA5
GPIO4_IO26<br />
 
SAI1_TX_BCLK<br />
EIM_AD05
USDHC1_CD_B<br />
 
ESAI_TX_CLK
GPIO4_IO26
 
SAI1_TX_BCLK
 
USDHC1_CD_BE
 
SAI_TX_CLK
 
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-PCM-CLK in SOM with WiFi/BT module
|-
|-
| 191
| 191
Line 2,160: Line 2,795:
| CSI-DATA4
| CSI-DATA4
| CSI_DATA04
| CSI_DATA04
| USDHC2_DATA4<br />
| USDHC2_DATA4
ECSPI1_SCLK<br />
 
EIM_AD04<br />
ECSPI1_SCLK
GPIO4_IO25<br />
 
SAI1_TX_SYNC<br />
EIM_AD04
USDHC1_WP<br />
 
GPIO4_IO25
 
SAI1_TX_SYNC
 
USDHC1_WP
 
ESAI_TX_FS
ESAI_TX_FS
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-PCM-SYNC in SOM with WiFi/BT module
|-
|-
| 192
| 192
Line 2,173: Line 2,816:
| CSI-DATA3
| CSI-DATA3
| CSI_DATA03
| CSI_DATA03
| USDHC2_DATA3<br />
| USDHC2_DATA3
ECSPI2_MISO<br />
 
EIM_AD03<br />
ECSPI2_MISO
GPIO4_IO24<br />
 
SAI1_RX_BCLK<br />
EIM_AD03
UART5_CTS_B<br />
 
GPIO4_IO24
 
SAI1_RX_BCLK
 
UART5_CTS_B
 
ESAI_RX_CLK
ESAI_RX_CLK
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-CTS in SOM with WiFi/BT module
|-
|-
| 193
| 193
Line 2,186: Line 2,837:
| CSI-DATA1
| CSI-DATA1
| CSI_DATA01
| CSI_DATA01
| USDHC2_DATA1<br />
| USDHC2_DATA1
ECSPI2_SS0<br />
 
EIM_AD01<br />
ECSPI2_SS0
GPIO4_IO22<br />
 
SAI1_MCLK<br />
EIM_AD01
UART5_RX<br />
 
GPIO4_IO22
 
SAI1_MCLK
 
UART5_RX
 
ESAI_RX_HF_CLK
ESAI_RX_HF_CLK
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-TXD in SOM with WiFi/BT module
|-
|-
| 194
| 194
Line 2,199: Line 2,858:
| CSI-DATA2
| CSI-DATA2
| CSI_DATA02
| CSI_DATA02
| USDHC2_DATA2<br />
| USDHC2_DATA2
ECSPI2_MOSI<br />
 
EIM_AD02<br />
ECSPI2_MOSI
GPIO4_IO23<br />
 
SAI1_RX_SYNC<br />
EIM_AD02
UART5_RTS_B<br />
 
GPIO4_IO23
 
SAI1_RX_SYNC
 
UART5_RTS_B
 
ESAI_RX_FS
ESAI_RX_FS
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-RTS in SOM with WiFi/BT module
|-
|-
| 195
| 195
Line 2,212: Line 2,879:
| CSI-DATA0
| CSI-DATA0
| CSI_DATA00
| CSI_DATA00
| USDHC2_DATA0<br />
| USDHC2_DATA0
ECSPI2_SCLK<br />
 
EIM_AD00<br />
ECSPI2_SCLK
GPIO4_IO21<br />
 
SRC_INT_BOOT<br />
EIM_AD00
UART5_TX<br />
 
GPIO4_IO21
 
SRC_INT_BOOT
 
UART5_TX
 
ESAI_TX_HF_CLK
ESAI_TX_HF_CLK
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-RXD in SOM with WiFi/BT module
|-
|-
| 196
| 196
Line 2,232: Line 2,907:
| CSI-HSYNC
| CSI-HSYNC
| CSI_HSYNC
| CSI_HSYNC
| USDHC2_CMD<br />
| USDHC2_CMD
I2C2_SCL<br />
 
EIM_LBA_B<br />
I2C2_SCL
GPIO4_IO20<br />
 
PWM8_OUT<br />
EIM_LBA_B
UART6_CTS_B<br />
 
GPIO4_IO20
 
PWM8_OUT
 
UART6_CTS_B
 
ESAI_TX1
ESAI_TX1
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
WLAN-HWAKE in SOM with WiFi/BT module
|-
|-
| 198
| 198
Line 2,245: Line 2,928:
| CSI-VSYNC
| CSI-VSYNC
| CSI_VSYNC
| CSI_VSYNC
| SDHC2_CLK<br />
| SDHC2_CLK
I2C2_SDA<br />
 
EIM_RW<br />
I2C2_SDA
GPIO4_IO19<br />
 
PWM7_OUT<br />
EIM_RW
UART6_RTS_B<br />
 
GPIO4_IO19
 
PWM7_OUT
 
UART6_RTS_B
 
ESAI_TX4_RX1
ESAI_TX4_RX1
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
| Video CMOS sensor signal or universal GPIO with 3.3V logic levels.
BT-HWAKE in SOM with WiFi/BT module
|-
|-
| 199
| 199

Latest revision as of 12:55, 31 October 2023

VisionSOM-6ULL Datasheet and Pinout

General description

The VisionSOM-6ULL family is a SODIMM-sized SoM based on the NXP i.MX6 ULL application processor which features an advanced implementation of a single ARM Cortex-A7 core (at speeds up to 900MHz).

The VisionSOM-6ULL is a low power highly integrated SoM (System on Module) featuring high computation power and 802.11b/g/n Wi-Fi and Bluetooth v5.1 connectivity. The option of integrated, fully certified Wi-Fi and Bluetooth module simplifies the carrier board design and is ideally suited for wireless application. The VisionSOM-6ULL provides a variety memory configuration including flexible range of DDR3L, NAND, eMMC and SD memory card that meets our customers requirements.

The SoM supports connections to a variety of interfaces: two high-speed USB on-the-go with PHY, dual Ethernet, audio, display with touch panel and serial interfaces. In addition, the system supports industrial grade targeting embedded application.

SOMLabs also provides a complete hardware and software development board for the SoM in the form of a carrier board and optional TFT display and touch panel.

Applications

  • Industrial embedded Linux computer
  • Home Appliances
  • Home Automation – Smart Home
  • Human-machine Interfaces (HMI)
  • Point-of-sales (POS) terminals
  • Cash Register
  • 2D barcode scanners and printers
  • Smart grid infrastructure
  • IoT gateways
  • Residential gateways
  • Machine vision equipment
  • Robotics
  • Fitness/outdoor equipment

Features

  • Powered by NXP i.MX 6ULL application processor
  • Core clock up to 900MHz
  • Up to 512MB SDRAM DDR3L
  • Up to 512MB NAND Flash / 32GB eMMC / uSD memory card
  • Optional Murata 802.11b/g/n Wi-Fi and Bluetooth v5.2 module
  • Power-efficient and cost-optimized solution
  • Ideal for industrial IoT and embedded applications
  • Integrated security features

Pictures of SOM versions

Version Photo
eMMC
micro-SD
NAND Flash
Wi-Fi is available for all memory variants configurations.

Ordering info

SLSN6CpuType_Clock_RamSize_FlashSize_SF_TEMP_V
SLSProduct type
SLS - System on Module
NSOM Name
1 - VisionSOM SODIMM200
6CPU Family
6 - i.MX6
CpuTypeCPU Type
Y0 - i.MX6 ULL Y0
Y1 - i.MX6 ULL Y1
Y2 - i.MX6 ULL Y2
ClockCPU Clock Speed
528C - 528MHz
792C - 792MHz
900C - 900MHz
RamSizeDDR3 RAM Size
64R - 64MB
128R - 128MB
256R - 256MB
512R - 512MB
FlashSizeFlash Size Type and Density
SD - MicroSD connector
128N - 128MB NAND
256N - 256MB NAND
512N - 512MB NAND
04GE - 4GB eMMC
08GE - 8GB eMMC
16GE - 16GB eMMC
32GE - 32GB eMMC
SFSpecial Features
0SF - No Special Features
1WB - Built-in 802.11b/g/n Wi-Fi and Bluetooth v5.1 Module
TEMPOperating Temperature
C - Consumer: 0 to +70 C
E - Extended with Wi-Fi: -25 to +70 C
I - Industrial: -40 to +85 C
VSOM Version
A - Version 1.0
B - Version 1.1

Block Diagram

Operating ranges

Parameter Value Unit Comment
Power Supply
5.0
V
 Connected to +5VIN SODIMM pin
Input GPIO voltage
3.3
V
 -
Environment temperature1
-40…+85
 oC Industrial range w/o WiFi module
-25…+70
 Industrial range with WiFi module
0…+70
 Consumer range

Note:
1. Maximum MPU junction temperature is +105oC (industrial version) or +95oC (consumer version).

Electrical parameters

SOM
signal name 		Parameter Value Units
Min. Typ. Max.
+5VIN Supply Voltage 4.0 5.0 5.5 V
+5VIN Total Supply Current1 - 115 155 mA
VGPIO GPIO Input Voltage 0 3.3 3.62 V
+3.3VOUT SOM Internal LDO
Output Current 		- - 0.5 A
USB-OTGx-VBUS USB Supply 4.40 - 5.5 V
VDD-COIN-3V SNVS Backup
Battery Supply 		2.66 - 3.6 V
- ADC Inputs Voltage 0 - 3.3 V

Notes:
1. Excluding external load connected to +3.3VOUT lines.
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.

SOM pinout (v1.1 and v1.2)

Important notes
1. Detail pin configurations description you can find, edit and arrange in dedicated MEX files (with free "i.MX Pin Tool" configurational tool): VisionSOM-6ULL without WiFi module and no SDIO1 on edge connector or VisionSOM-6ULL without WiFi module and with SDIO1 on edge connector or VisionSOM-6ULL witht WiFi module on-board.
2. In module version v1.1 the LCD-DATAxx pins are internally used for boot sequence configuration. We recommend to use LCD-DATAxx lines as outputs or using eFuse boot configuration.
3. In module version v1.2 equipped with NAND Flash the LCD-DATAxx pins are internally used for boot sequence configuration (like in v1.1). We recommend to use LCD-DATAxx lines as outputs or using eFuse boot configuration.
4. In module version v1.2 equipped with eMMC the boot sequence configuration is stored in eFuse (OTP memory in MPU). All LCD-DATAxx pins can be used freely like all others GPIOs.

SODIMM PIN Functional

domain

Function name i.MX6 UltraLite/

ULL Pad Name

Alternate functions Description (refer to i.MX6 UltraLite/ULL manuals for details)
1 Power GND - - -
2 Power GND - - -
3 Ctrl PMIC-STBY-REQ CCM_PMIC_STBY_REQ - Output, leave open if not used.
4 Ctrl MX6-POR-B - - External warm reset input, active L.
5 Ctrl PMIC-ON-REQ SNVS_PMIC_ON_REQ - Output, leave open if not used.
6 Power VDD-SNVS-3V3 VDD_SNVS_IN - SNVS backup power supply must be held between 2.9V and 3.3V if the system requires keeping real time and other data on OFF state. Internally connected to +3.3V, leave open.
7 BOOT BOOT-MODE1 BOOT_MODE1 GPIO5_IO11 BOOT-MODE1 BOOT-MODE0

00 boot from fuses (default)

01 serial downloader

10 internal boot

11 reserved

8 Power VDD-COIN-3V VDD_SNVS_IN - Optional external coin battery for SNVS power domain, must be held between 2.9V and 3.3V if the system requires keeping real time and other data on OFF state.

Leave open if not used.

9 BOOT BOOT-MODE0 BOOT_MODE0 GPIO5_IO10 BOOT-MODE1 BOOT-MODE0

00 boot from fuses (default)

01 serial downloader

10 internal boot

11 reserved

10 GPIO-SNVS SNVS-TAMPER9 SNVS_TAMPER9 GPIO5_IO09 Tamper input (SNVS power domain) or GPIO 3.3V.
11 USB USB-OTG2-VBUS USB_OTG2_VBUS - +5V USB bus. Leave open if not used.
12 GPIO-SNVS SNVS-TAMPER5 SNVS_TAMPER5 GPIO5_IO05 Tamper input (SNVS power domain) or GPIO 3.3V.
13 USB USB-OTG1-VBUS USB_OTG1_VBUS - +5V USB bus. Leave open if not used.
14 Ctrl ONOFF SRC_RESET_B Input for power interrupt generation. Leave open if not used.
15 Power GND - - -
16 Ctrl POR-B POR_B - Cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal and external signals are considered active low).

17 Power GND - - -
18 GPIO-SNVS SNVS-TAMPER8 SNVS_TAMPER8 GPIO5_IO08 Tamper input (SNVS power domain) or GPIO 3.3V.
19 USB USB-OTG2-DP USB_OTG2_DP - Leave open if not used.
20 Power GND - - -
21 USB USB-OTG2-DN USB_OTG2_DN - Leave open if not used.
22 Power GND - - -
23 Power GND - - -
24 GPIO-SNVS SNVS-TAMPER7 SNVS_TAMPER7 GPIO5_IO07 Tamper input (SNVS power domain) or GPIO 3.3V.
25 USB USB-OTG1-DP USB_OTG1_DP - Leave open if not used.
26 Power GND - - -
27 USB USB-OTG1-DN USB_OTG1_DN - Leave open if not used.
28 Power GND - - -
29 Power GND - - -
30 GPIO-SNVS SNVS-TAMPER4 SNVS_TAMPER4 GPIO5_IO04 Tamper input (SNVS power domain) or GPIO 3.3V.
31 USB nUSB-OTG-CHD USB_OTG1_CHD_B - Leave open if not used.
32 GPIO-SNVS SNVS-TAMPER1 SNVS_TAMPER1 GPIO5_IO01 Tamper input (SNVS power domain) or GPIO 3.3V.
33 JTAG JTAG-MOD JTAG_MOD - Leave open if not used.
34 GPIO-SNVS SNVS-TAMPER3 SNVS_TAMPER3 GPIO5_IO03 Tamper input (SNVS power domain) or GPIO 3.3V.
35 Power GND - - -
36 GPIO-SNVS SNVS-TAMPER0 SNVS_TAMPER0 GPIO5_IO00 Tamper input (SNVS power domain) or GPIO 3.3V.
37 CLK1-N CCM_CLK1_N - General purpose differential high speed clock input/output.

Leave open if not used.

38 Power GND - - -
39 CLK1-P CCM_CLK1_P - General purpose differential high speed clock input/output.

Leave open if not used.

40 Power GND - - -
41 Power GND - - -
42 GPIO-SNVS SNVS-TAMPER6 SNVS_TAMPER6 GPIO5_IO06 Tamper input (SNVS power domain) or GPIO 3.3V.
43 JTAG JTAG-TDI JTAG_TDI - JTAG TDI input line or GPIO.
44 GPIO-SNVS SNVS-TAMPER2 SNVS_TAMPER2 GPIO5_IO02 Tamper input (SNVS power domain) or GPIO 3.3V.
45 GPIO GPIO-8 GPIO1_IO08 PWM1_OUT

WDOG1_WDOG_B

SPDIF_OUT

CSI_VSYNC

USDHC2_VSELECT

CCM_PMIC_RDY

UART5_RTS_B

Universal GPIO with 3.3V logic levels.
46 JTAG JTAG-TMS JTAG_TMS - JTAG TMS input line or GPIO.
47 GPIO GPIO-4 GPIO1_IO04 ENET1_REF_CLK1

PWM3_OUT

USB_OTG1_PWR

USDHC1_RESET_B

ENET2_1588_EVENT0_IN

UART5_TX

Universal GPIO with 3.3V logic levels.
48 JTAG JTAG-nTRST JTAG_TRST_B - JTAG TRST input line (active L) or GPIO.
49 GPIO GPIO-5 GPIO1_IO05 ENET2_REF_CLK2

PWM4_OUT

ANATOP_OTG2_ID

CSI_FIELD

USDHC1_VSELECT

ENET2_1588_EVENT0_OUT

UART5_RX

Universal GPIO with 3.3V logic levels.

WLAN-ENABLE in SOM with WiFi/BT module

50 Power GND - - -
51 Power GND - - -
52 JTAG JTAG-TDO JTAG_TDO - JTAG TDO output line or GPIO.
53 GPIO GPIO-7 GPIO1_IO07 ENET1_MDC

ENET2_MDC

USB_OTG_HOST_MODE

CSI_PIXCLK

USDHC2_CD_BCCM_STOP

UART1_RTS_B

Universal GPIO with 3.3V logic levels.
54 JTAG JTAG-TCK JTAG_TCK - JTAG TCK input line or GPIO.

Connected to JTAG-TCK line (via separating resistor 10k).

55 GPIO GPIO-3 GPIO1_IO03 I2C1_SDA

GPT1_COMPARE3

USB_OTG2_OC

USDHC1_CD_B

CCM_DI0_EXT_CLK

SRC_TESTER_ACK

Universal GPIO with 3.3V logic levels.
56 GPIO GPIO-9 GPIO1_IO09 PWM2_OUT

WDOG1_WDOG_ANY

SPDIF_IN

CSI_HSYNC

USDHC2_RESET_B

USDHC1_RESET_B

UART5_CTS_B

Universal GPIO with 3.3V logic levels.
57 COM-GPIO UART1-TXD UART1_TX_DATA ENET1_RDATA02

I2C3_SCL

CSI_DATA02

GPT1_COMPARE1

GPIO1_IO16

SPDIF_OUT

UART5_TX

Default: UART1 TxD output or universal GPIO with 3.3V logic levels.
58 GPIO GPIO-2 GPIO1_IO02 I2C1_SCL

GPT1_COMPARE2

USB_OTG2_PWR

ENET1_REF_CLK_25M

USDHC1_WPS

DMA_EXT_EVENT00

SRC_ANY_PU_RESET

UART1_TX

Universal GPIO with 3.3V logic levels.
59 Power GND - - -
60 Power GND - - -
61 GPIO GPIO-6 GPIO1_IO06 ENET1_MDIO

ENET2_MDIO

USB_OTG_PWR_WAKE

CSI_MCLK

USDHC2_WPCCM_WAIT

CCM_REF_EN_B

UART1_CTS_B

Universal GPIO with 3.3V logic levels.
62 GPIO GPIO-1 GPIO1_IO01 I2C2_SDA

GPT1_COMPARE1

USB_OTG1_OC

ENET2_REF_CLK2

MQS_LEFT

ENET1_1588_EVENT0_OUT

SRC_EARLY_RESET

WDOG1_WDOG_B

Universal GPIO with 3.3V logic levels.
63 COM-GPIO UART1-RXD UART1_RX_DATA ENET1_RDATA03

I2C3_SDA

CSI_DATA03

GPT1_CLK

GPIO1_IO17

SPDIF_IN

UART5_RX

Default: UART1 RxD input or universal GPIO with 3.3V logic levels.
64 GPIO GPIO-0 GPIO1_IO00 I2C2_SCL

GPT1_CAPTURE1

ANATOP_OTG1_ID

ENET1_REF_CLK1

MQS_RIGHT

ENET1_1588_EVENT0_IN

SRC_SYSTEM_RESET

WDOG3_WDOG_B

Universal GPIO with 3.3V logic levels.
65 COM-GPIO UART2-TXD UART2_TX_DATA ENET1_TDATA02

I2C4_SCL

CSI_DATA06

GPT1_CAPTURE1

GPIO1_IO20

ECSPI3_SS0

Default: UART2 TxD output or universal GPIO with 3.3V logic levels.
66 COM-GPIO UART1-CTS UART1_CTS_B ENET1_RX_CLK

USDHC1_WP

CSI_DATA04

ENET2_1588_EVENT1_IN

GPIO1_IO18

USDHC2_WP

UART5_CTS_B

Default: UART1 CTS output or universal GPIO with 3.3V logic levels.
67 COM-GPIO UART2-RXD UART2_RX_DATA ENET1_TDATA03

I2C4_SDA

CSI_DATA07

GPT1_CAPTURE2

GPIO1_IO21

SJC_DONE

ECSPI3_SCLK

Default: UART2 RxD input or universal GPIO with 3.3V logic levels.
68 COM-GPIO UART5-RXD UART5_RX_DATA ENET2_COL

I2C2_SDA

CSI_DATA15

CSU_CSU_INT_DEB

GPIO1_IO31

ECSPI2_MISO

EPDC_PWRCTRL03

Default: UART5 RxD input or universal GPIO with 3.3V logic levels.
69 COM-GPIO UART3-TXD UART3_TX_DATA ENET2_RDATA02

CSI_DATA01

UART2_CTS_B

GPIO1_IO24

SJC_JTAG_ACT

Default: UART3 TxD input or universal GPIO with 3.3V logic levels.
70 Power GND - - -
71 Power GND - - -
72 COM-GPIO UART2-CTS UART2_CTS_B ENET1_CRS

FLEXCAN2_TXCSI_DATA08

GPT1_COMPARE2

GPIO1_IO22

SJC_DE_B

ECSPI3_MOSI

Default: UART2 CTS output or universal GPIO with 3.3V logic levels.
73 COM-GPIO UART3-RXD UART3_RX_DATA ENET2_RDATA03

CSI_DATA00

UART2_RTS_B

GPIO1_IO25

EPIT1_OUT

Default: UART3 RxD input or universal GPIO with 3.3V logic levels.
74 COM-GPIO UART1-RTS UART1_RTS_B ENET1_TX_ER

USDHC1_CD_BCSI_DATA05

ENET2_1588_EVENT1_OUT

GPIO1_IO19

USDHC2_CD_B

UART5_RTS_B

Default: UART1 RTS input or universal GPIO with 3.3V logic levels.
75 COM-GPIO UART4-TXD UART4_TX_DATA ENET2_TDATA02

I2C1_SCL

CSI_DATA12

CSU_CSU_ALARM_AUT02

GPIO1_IO28

ECSPI2_SCLK

Default: UART4 TxD output or universal GPIO with 3.3V logic levels.
76 COM-GPIO UART3-CTS UART3_CTS_B ENET2_RX_CLK

FLEXCAN1_TX

CSI_DATA10

ENET1_1588_EVENT1_IN

GPIO1_IO26

EPIT2_OUT

Default: UART3 CTS output or universal GPIO with 3.3V logic levels.
77 COM-GPIO UART4-RXD UART4_RX_DATA ENET2_TDATA03

I2C1_SDA

CSI_DATA13

CSU_CSU_ALARM_AUT01

GPIO1_IO29

ECSPI2_SS0

EPDC_PWRCTRL01

Default: UART4 RxD input or universal GPIO with 3.3V logic levels.
78 COM-GPIO UART2-RTS UART2_RTS_B ENET1_COL

FLEXCAN2_RX

CSI_DATA09

GPT1_COMPARE3

GPIO1_IO23

SJC_FAIL

ECSPI3_MISO

Default: UART2 RTS input or universal GPIO with 3.3V logic levels.
79 COM-GPIO UART5-TXD UART5_TX_DATA GPIO1_IO30

ECSPI2_MOSI

EPDC_PWRCTRL02

ENET2_CRS

I2C2_SCL

CSI_DATA14

CSU_CSU_ALARM_AUT00

Default: UART5 TxD output or universal GPIO with 3.3V logic levels.
80 COM-GPIO UART3-RTS UART3_RTS_B ENET2_TX_ER

FLEXCAN1_RX

CSI_DATA11

ENET1_1588_EVENT1_OUT

GPIO1_IO27

WDOG1_WDOG_B

Default: UART3 RTS input or universal GPIO with 3.3V logic levels.
81 Power GND - - -
82 Power GND - - -
83 NC - - - -
84 Power GND - - -
85 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
86 NC - - - -
87 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
88 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
89 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
90 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
91 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
92 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
93 Power +3.3VOUT - - +3.3V generated by SOM's LDO.
94 NC - - - -
95 NC - - - -
96 Power +5VIN - - +4.0-5.5V input power supply.
97 Ethernet ENET1-RXD0 ENET1_RX_DATA0 UART4_RTS_B

PWM1_OUT

CSI_DATA16

FLEXCAN1_TX

GPIO2_IO00

KPP_ROW00

USDHC1_LCTL

EPDC_SDCE04

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
98 Power +5VIN - - +4.0-5.5V input power supply.
99 Ethernet ENET1-RXD1 ENET1_RX_DATA1 UART4_CTS_B

PWM2_OUT

CSI_DATA17

FLEXCAN1_RX

GPIO2_IO01

KPP_COL00

USDHC2_LCTL

EPDC_SDCE05

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
100 Power +5VIN - - +4.0-5.5V input power supply.
101 Ethernet ENET1-CRS-DV ENET1_RX_EN UART5_RTS_B

CSI_DATA18

FLEXCAN2_TX

GPIO2_IO02

KPP_ROW01

USDHC1_VSELECT

EPDC_SDCE06

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
102 Power +5VIN +4.0-5.5V input power supply.
103 Power GND - - -
104 Power +5VIN +4.0-5.5V input power supply.
105 Ethernet ENET2-TX-CLK ENET2_TX_CLK UART8_CTS_B

ECSPI4_MISO

ENET2_REF_CLK2

GPIO2_IO14

KPP_ROW07

ANATOP_OTG2_ID

EPDC_SDDO14

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.

10R resistor connected in series.

106 Power +5VIN +4.0-5.5V input power supply.
107 Power GND - - -
108 Power +5VIN +4.0-5.5V input power supply.
109 Ethernet ENET2-RXER ENET2_RX_ER UART8_RTS_B

ECSPI4_SS0

EIM_ADDR25

GPIO2_IO15

KPP_COL07

WDOG1_WDOG_ANY

EPDC_SDDO15

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.

Connected to WDOG-B line.

110 Power +5VIN - - +4.0-5.5V input power supply.
111 Ethernet ENET2-RXD0 ENET2_RX_DATA0 UART6_TX

I2C3_SCL

ENET1_MDIO

GPIO2_IO08

KPP_ROW04

USB_OTG1_PWR

EPDC_SDDO08

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
112 Power +5VIN - - +4.0-5.5V input power supply.
113 Ethernet ENET2-RXD1 ENET2_RX_DATA1 UART6_RX

I2C3_SDA

ENET1_MDC

GPIO2_IO09

KPP_COL04

USB_OTG1_OCE

PDC_SDDO09

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
114 Ethernet ENET1-TXEN ENET1_TX_EN UART6_RTS_B

PWM6_OUT

CSI_DATA21

ENET2_MDC

GPIO2_IO05

KPP_COL02

WDOG2_WDOG_RST_B_DEB

EPDC_SDCE09

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
115 Power GND - - -
116 Power GND - - -
117 Ethernet ENET2-CRS-DV ENET2_RX_EN UART7_TX

I2C4_SCL

EIM_ADDR26

GPIO2_IO10

KPP_ROW05

ENET1_REF_CLK_25M

EPDC_SDDO10

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
118 Ethernet ENET1-TX-CLK ENET1_TX_CLK UART7_CTS_B

PWM7_OUT

CSI_DATA22

ENET1_REF_CLK1

GPIO2_IO06

KPP_ROW03

GPT1_CLK

EPDC_SDOED

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.

10R resistor connected in series.

119 Ethernet ENET2-TXD1 ENET2_TX_DATA1 UART8_TX

ECSPI4_SCLK

EIM_EB_B03

GPIO2_IO12

KPP_ROW06

USB_OTG2_PWR

EPDC_SDDO12

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
120 Power GND - - -
121 Ethernet ENET2-TXEN ENET2_TX_EN UART8_RX

ECSPI4_MOSI

EIM_ACLK_FREERUN

GPIO2_IO13

KPP_COL06

USB_OTG2_OC

EPDC_SDDO13

122 Ethernet ENET1-TXD0 ENET1_TX_DATA0 UART5_CTS_B

CSI_DATA19

FLEXCAN2_RX

GPIO2_IO03

KPP_COL01

USDHC2_VSELECT

EPDC_SDCE07

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
123 Ethernet ENET2-TXD0 ENET2_TX_DATA0 UART7_RX

I2C4_SDA

EIM_EB_B02

GPIO2_IO11

KPP_COL05

EPDC_SDDO11

Ethernet MAC2-PHY interface signal or universal GPIO with 3.3V logic levels.
124 Ethernet ENET1-TXD1 ENET1_TX_DATA1 UART6_CTS_B

PWM5_OUT

CSI_DATA20

ENET2_MDIO

GPIO2_IO04

KPP_ROW02

WDOG1_WDOG_RST_B_DEB

EPDC_SDCE08

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
125 Power GND - - -
126 Ethernet ENET1-RXER ENET1_RX_ER UART7_RTS_B

PWM8_OUT

CSI_DATA23

EIM_CRE

GPIO2_IO07

KPP_COL03

GPT1_CAPTURE2

EPDC_SDOEZ

Ethernet MAC1-PHY interface signal or universal GPIO with 3.3V logic levels.
127 Power GND - - -
128 Power GND - - -
129 LCD LCD-DATA21 LCD_DATA21 UART8_RX

ECSPI1_SS0

CSI_DATA13

EIM_DATA13

GPIO3_IO26

SRC_BT_CFG29

USDHC2_DATA1

EPDC_SDCE01

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

130 Power GND - - -
131 LCD LCD-DATA22 LCD_DATA22 MQS_RIGHT

ECSPI1_MOSI

CSI_DATA14

EIM_DATA14

GPIO3_IO27

SRC_BT_CFG30

USDHC2_DATA2

USDHC2_DATA2

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

132 Power GND - - -
133 LCD LCD-DATA17 LCD_DATA17 UART7_RX

CSI_DATA00

EIM_DATA09

GPIO3_IO22

SRC_BT_CFG25

USDHC2_DATA7

EPDC_GDSP

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

134 LCD LCD-DATA23 LCD_DATA23 MQS_LEFT

ECSPI1_MISO

CSI_DATA15

EIM_DATA15

GPIO3_IO28

SRC_BT_CFG31

USDHC2_DATA3

EPDC_SDCE03

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

135 Power GND - - -
136 Power GND - - -
137 LCD LCD-DATA18 LCD_DATA18 PWM5_OUT

CA7_MX6ULL_EVENTO

CSI_DATA10

EIM_DATA10

GPIO3_IO23

SRC_BT_CFG26

USDHC2_CMD

EPDC_BDR01

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

138 LCD LCD-DATA19 LCD_DATA19 PWM6_OUT

WDOG1_WDOG_ANY

CSI_DATA11

EIM_DATA11

GPIO3_IO24

SRC_BT_CFG27

USDHC2_CLK

EPDC_VCOM00

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

139 LCD LCD-DATA13 LCD_DATA13 SAI3_TX_BCLK

CSI_DATA21

EIM_DATA05

GPIO3_IO18

SRC_BT_CFG13

USDHC2_RESET_B

EPDC_BDR00

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

140 LCD LCD-DATA20 LCD_DATA20 UART8_TX

ECSPI1_SCLK

CSI_DATA12

EIM_DATA12

GPIO3_IO25

SRC_BT_CFG28

USDHC2_DATA0

EPDC_VCOM01

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

141 LCD LCD-DATA14 LCD_DATA14 SAI3_RX_DATA

CSI_DATA22

EIM_DATA06

GPIO3_IO19

SRC_BT_CFG14

USDHC2_DATA4

EPDC_SDSHR

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

142 LCD LCD-DATA15 LCD_DATA15 SAI3_TX_DATA

CSI_DATA23

EIM_DATA07

GPIO3_IO20

SRC_BT_CFG15

USDHC2_DATA5

EPDC_GDRL

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

143 LCD LCD-DATA8 LCD_DATA08 SPDIF_IN

CSI_DATA16

EIM_DATA00

GPIO3_IO13

SRC_BT_CFG08

FLEXCAN1_TX

EPDC_PWRIRQ

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

144 LCD LCD-DATA16 LCD_DATA16 UART7_TX

CSI_DATA01

EIM_DATA08

GPIO3_IO21

SRC_BT_CFG24

USDHC2_DATA6

EPDC_GDCLK

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

145 LCD LCD-DATA9 LCD_DATA09 SAI3_MCLK

CSI_DATA17

EIM_DATA01

GPIO3_IO14

SRC_BT_CFG09

FLEXCAN1_RX

EPDC_PWRWAKE

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

146 Power GND - - -
147 Power GND - - -
148 LCD LCD-DATA11 LCD_DATA11 SAI3_RX_BCLK

CSI_DATA19

EIM_DATA03

GPIO3_IO16

SRC_BT_CFG11

FLEXCAN2_RX

EPDC_PWRSTAT

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

149 LCD LCD-DATA5 LCD_DATA05 UART8_RTS_B

ENET2_1588_EVENT2_OUT

SPDIF_OUT

GPIO3_IO10

SRC_BT_CFG05

ECSPI1_SS1

EPDC_SDDO05

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

150 LCD LCD-DATA12 LCD_DATA12 SAI3_TX_SYNC

CSI_DATA20

EIM_DATA04

GPIO3_IO17

SRC_BT_CFG12

ECSPI1_RDY

EPDC_PWRCTRL00

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

151 LCD LCD-DATA6 LCD_DATA06 UART7_CTS_B

ENET2_1588_EVENT3_IN

SPDIF_LOCK

GPIO3_IO11

SRC_BT_CFG06

ECSPI1_SS2

EPDC_SDDO06

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

152 LCD LCD-DATA10 LCD_DATA10 SAI3_RX_SYNC

CSI_DATA18

EIM_DATA02

GPIO3_IO15

SRC_BT_CFG10

FLEXCAN2_TX

EPDC_PWRCOM

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

153 LCD LCD-DATA0 LCD_DATA00 PWM1_OUT

ENET1_1588_EVENT2_IN

I2C3_SDA

GPIO3_IO05

SRC_BT_CFG00

SAI1_MCLK

EPDC_SDDO00

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

154 LCD LCD-DATA3 LCD_DATA03 PWM4_OUT

ENET1_1588_EVENT3_OUT

I2C4_SCL

GPIO3_IO08

SRC_BT_CFG03

SAI1_RX_DATA

EPDC_SDDO03

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

155 LCD LCD-DATA1 LCD_DATA01 PWM2_OUT

ENET1_1588_EVENT2_OUT

I2C3_SCL

GPIO3_IO06

SRC_BT_CFG01

SAI1_TX_SYNC

EPDC_SDDO01

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

156 Power GND - - -
157 LCD LCD-RESET LCD_RESET LCDIF_CS

CA7_MX6ULL_EVENT

ISAI3_TX_DATA

WDOG1_WDOG_ANY

GPIO3_IO04

ECSPI2_SS3

EPDC_GDOE

LCD interface signal or universal GPIO with 3.3V logic levels.
158 LCD LCD-DATA4 LCD_DATA04 UART8_CTS_B

ENET2_1588_EVENT2_IN

SPDIF_SR_CLK

GPIO3_IO09

SRC_BT_CFG04

SAI1_TX_DATA

EPDC_SDDO04

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

159 Power GND - - -
160 LCD LCD-HSYNC LCD_HSYNC LCDIF_RS

UART4_CTS_B

SAI3_TX_BCLK

WDOG3_WDOG_RST_B_DEB

GPIO3_IO02

ECSPI2_SS1

EPDC_SDOE

LCD interface signal or universal GPIO with 3.3V logic levels.
161 LCD LCD-CLK LCD_CLK LCDIF_WR_RWN

UART4_TX

SAI3_MCLK

EIM_CS2_B

GPIO3_IO00

WDOG1_WDOG_RST_B_DEB

EPDC_SDCLK

LCD interface signal or universal GPIO with 3.3V logic levels.

10R resistor connected in series.

162 LCD LCD-VSYNC LCD_VSYNC LCDIF_BUSY

UART4_RTS_B

SAI3_RX_DATA

WDOG2_WDOG_B

GPIO3_IO03

ECSPI2_SS2

EPDC_SDCE00

LCD interface signal or universal GPIO with 3.3V logic levels.
163 LCD LCD-ENABLE LCD_ENABLE LCDIF_RD_E

UART4_RX

SAI3_TX_SYNC

EIM_CS3_B

GPIO3_IO01

ECSPI2_RDY

EPDC_SDLE

LCD interface signal or universal GPIO with 3.3V logic levels.
164 LCD LCD-DATA2 LCD_DATA02 PWM3_OUT

ENET1_1588_EVENT3_IN

I2C4_SDA

GPIO3_IO07

SRC_BT_CFG02

SAI1_TX_BCLK

EPDC_SDDO02

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

165 Power GND - - -
166 LCD LCD-DATA7 LCD_DATA07 UART7_RTS_B

ENET2_1588_EVENT3_OUT

SPDIF_EXT_CLK

GPIO3_IO12

SRC_BT_CFG07

ECSPI1_SS3

EPDC_SDDO07

LCD interface signal or universal GPIO with 3.3V logic levels.

Internally used as boot configuration input (Notes 2, 3 & 4).

167 SDIO SDIO1-D0 SD1_DATA0 GPT2_COMPARE3

SAI2_TX_SYNC

FLEXCAN1_TX

EIM_ADDR21

GPIO2_IO18

ANATOP_OTG1_ID

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

Built-in internal pull-up 10k.

168 Power GND - - -
169 SDIO SDIO1-D3 SD1_DATA3 GPT2_CAPTURE2

SAI2_TX_DATA

FLEXCAN2_RX

EIM_ADDR24

GPIO2_IO21

CCM_CLKO2

ANATOP_OTG2_ID

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

Built-in internal pull-up 10k.


170 Power GND - - -
171 SDIO SDIO1-D1 SD1_DATA1 GPT2_CLK

SAI2_TX_BCLK

FLEXCAN1_RX

EIM_ADDR22

GPIO2_IO19

USB_OTG2_PWR

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

Built-in internal pull-up 10k.


172 Power GND - - -
173 SDIO SDIO1-CMD SD1_CMD GPT2_COMPARE1

SAI2_RX_SYNC

SPDIF_OUT

EIM_ADDR19

GPIO2_IO16

SDMA_EXT_EVENT00

USB_OTG1_PWR

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

Built-in internal pull-up 10k.


174 Power GND - - -
175 SDIO SDIO1-D2 SD1_DATA2 GPT2_CAPTURE1

SAI2_RX_DATA

FLEXCAN2_TX

EIM_ADDR23

GPIO2_IO20

CCM_CLKO1

USB_OTG2_OC

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

Built-in internal pull-up 10k.


176 Power GND - - -
177 Power GND - - -
178 Power GND - - -
179 SDIO SDIO1-CLK SD1_CLK GPT2_COMPARE2

SAI2_MCLK

SPDIF_IN

EIM_ADDR20

GPIO2_IO17

USB_OTG1_OC

SDIO interface signal or universal GPIO with 3.3V logic levels.

Used by WiFi/BT module if built-in SOM.

180 Power GND - - -
181 Power GND - - -
182 Power GND - - -
183 CSI CSI-PIXCLK CSI_PIXCLK USDHC2_WP

RAWNAND_CE3_B

I2C1_SCL

EIM_OE

GPIO4_IO18

SNVS_HP_VIO_5

UART6_RX

ESAI_TX2_RX3

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-WAKE in SOM with WiFi/BT module

184 Power GND - - -
185 Power GND - - -
186 CSI CSI-DATA6 CSI_DATA06 USDHC2_DATA6

ECSPI1_MOSI

EIM_AD06

GPIO4_IO27

SAI1_RX_DATA

USDHC1_RESET_BE

SAI_TX5_RX0

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-PCM-OUT in SOM with WiFi/BT module

187 CSI CSI-MCLK CSI_MCLK USDHC2_CD_B

RAWNAND_CE2_B

I2C1_SDA

EIM_CS0_B

GPIO4_IO17

SNVS_HP_VIO_5_CTL

UART6_TX

ESAI_TX3_RX2

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-ENABLE in SOM with WiFi/BT module

188 CSI CSI-DATA7 CSI_DATA07 USDHC2_DATA7

ECSPI1_MISO

EIM_AD07

GPIO4_IO28

SAI1_TX_DATA

USDHC1_VSELECT

ESAI_TX0

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-PCM-IN in SOM with WiFi/BT module

189 Power GND - - -
190 CSI CSI-DATA5 CSI_DATA05 USDHC2_DATA5

USDHC2_DATA5

EIM_AD05

GPIO4_IO26

SAI1_TX_BCLK

USDHC1_CD_BE

SAI_TX_CLK

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-PCM-CLK in SOM with WiFi/BT module

191 CSI CSI-DATA4 CSI_DATA04 USDHC2_DATA4

ECSPI1_SCLK

EIM_AD04

GPIO4_IO25

SAI1_TX_SYNC

USDHC1_WP

ESAI_TX_FS

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-PCM-SYNC in SOM with WiFi/BT module

192 CSI CSI-DATA3 CSI_DATA03 USDHC2_DATA3

ECSPI2_MISO

EIM_AD03

GPIO4_IO24

SAI1_RX_BCLK

UART5_CTS_B

ESAI_RX_CLK

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-CTS in SOM with WiFi/BT module

193 CSI CSI-DATA1 CSI_DATA01 USDHC2_DATA1

ECSPI2_SS0

EIM_AD01

GPIO4_IO22

SAI1_MCLK

UART5_RX

ESAI_RX_HF_CLK

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-TXD in SOM with WiFi/BT module

194 CSI CSI-DATA2 CSI_DATA02 USDHC2_DATA2

ECSPI2_MOSI

EIM_AD02

GPIO4_IO23

SAI1_RX_SYNC

UART5_RTS_B

ESAI_RX_FS

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-RTS in SOM with WiFi/BT module

195 CSI CSI-DATA0 CSI_DATA00 USDHC2_DATA0

ECSPI2_SCLK

EIM_AD00

GPIO4_IO21

SRC_INT_BOOT

UART5_TX

ESAI_TX_HF_CLK

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-RXD in SOM with WiFi/BT module

196 Power CSI-VREF - - Leave open if not used.
197 CSI CSI-HSYNC CSI_HSYNC USDHC2_CMD

I2C2_SCL

EIM_LBA_B

GPIO4_IO20

PWM8_OUT

UART6_CTS_B

ESAI_TX1

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

WLAN-HWAKE in SOM with WiFi/BT module

198 CSI CSI-VSYNC CSI_VSYNC SDHC2_CLK

I2C2_SDA

EIM_RW

GPIO4_IO19

PWM7_OUT

UART6_RTS_B

ESAI_TX4_RX1

Video CMOS sensor signal or universal GPIO with 3.3V logic levels.

BT-HWAKE in SOM with WiFi/BT module

199 Power GND - - -
200 Power GND - - -

Dimensions

Retrieved from "https://wiki.somlabs.com/index.php?title=VisionSOM-6ULL_Datasheet_and_Pinout&oldid=3500"