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VisionSOM-RT-ETH Datasheet and Pinout: Difference between revisions

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| VDD-COIN-3V
| VDD-COIN-3V
| SNVS Backup<br />Battery Supply
| SNVS Backup<br />Battery Supply
| 2.66
| 2.9
| -
| -
| 3.6
| 3.6
Line 256: Line 256:
|}
|}
Notes:<br />
Notes:<br />
1. Excluding external load connected to +3.3VOUT lines.<br />
1. Excluding external load connected to +3.3VOUT lines and with Ethernet PHY in stand-by mode.<br />
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.<br />


== Pinout ==
== Pinout ==
Important notes:<br />
Important notes:<br />
1. LCD_DATAxx pins are internally used for boot sequence configuration. We recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <br />
1. LCD_DATAxx pins can be used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. <b>Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions.</b> <br />
2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 model.
2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 MCU.<br />
3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).


{| class="wikitable"  
{| class="wikitable"  
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| -
| -
| M9
| M9
| Optional  external coin battery for SNVS power domain, must be held between 2.9V and  3.3V if the system requires keeping real time and other data on OFF  state.<br />    Leave open if not used.<br />    Parallel power supply for SNVS domain.<br />    Connected in parallel with the line VDD-SNVS-3V3.
| Optional  external coin battery for SNVS power domain, must be held between 2.9V and  3.6V if the system requires keeping real time and other data on OFF  state.<br />    Leave open if not used.<br />    Parallel power supply for SNVS domain.<br />    Connected in parallel with the line VDD-SNVS-3V3.
|- style="vertical-align:bottom;"
|- style="vertical-align:bottom;"
| 9
| 9
Line 1,478: Line 1,479:
2. MDC and MDIO lines are not used for PHY configuration.<br />
2. MDC and MDIO lines are not used for PHY configuration.<br />
3. Hardware interrupt (line INTRP/NAND_TREE of PHY) is not connected to MCU.<br />
3. Hardware interrupt (line INTRP/NAND_TREE of PHY) is not connected to MCU.<br />
4. The clock signal for Ethernet PHY (line ENET1.TX-CLK) is generated on GPIO_B1_10 (ball B13) of MCU.<br />


{| class="wikitable"  
{| class="wikitable"  
Line 1,527: Line 1,529:
| 1k pull-down
| 1k pull-down


|}
== On-board JTAG connector ==
The VisionSOM-RT-ETH is equipped with on-board JTAG connector.
[[File:VisionSOM-RT-ETH-JTAG.png|center]]
{| class="wikitable" style="vertical-align:middle;"
|-
! J600 connector pin
! JTAG signal
! SOM pin
|-
| 1
| VDD-3V3
| 85
|-
| 2
| JTAG-TMS
| 46
|-
| 3
| JTAG-TCK
| 54
|-
| 4
| JTAG-TDO
| 52
|-
| 5
| JTAG-TDI
| 43
|-
| 6
| JTAG-nTRST
| 48
|-
| 7
| POR-B
| 16
|-
| 8
| GND
| 28
|}
|}


== Dimensions ==
== Dimensions ==
[[File:visionSOM-RT-ETH-size.png|600px|center]]
[[File:visionSOM-RT-ETH-size.png|600px|center]]

Latest revision as of 11:23, 5 September 2025

VisionSOM-RT-ETH Datasheet and Pinout


General description

The VisionSOM-RT-ETH family is a SODIMM-sized SoM based on the NXP i.MX RT application processor which features an advanced implementation of a single ARM Cortex-M7 core (at speeds up to 600MHz).

The VisionSOM-RT-ETH is a low power highly integrated SoM (System-on-Module) featuring Ethernet PHY on-board, high computation performance, real-time functionality and MCU usability. High security enabled by AES-128, HAB and On-the-fly QSPI Flash Decryption together with 2D graphical acceleration make an ideally suited solution for home and industrial control systems, wireless application, communication solutions and real-time systems.

The system supports industrial grade targeting embedded application.

SoMLabs also provides a complete hardware and software development board for the SoM in the form of a carrier board and optional TFT display and touch panel.

Applications

  • Industrial embedded RTOS computer
  • Home Appliances
  • Home Automation – Smart Home
  • Human-machine Interfaces (HMI)
  • Point-of-sales (POS) terminals
  • Cash Register
  • 2D barcode scanners and printers
  • Smart grid Infrastructure
  • IoT gateways
  • Residential getaways
  • Machine vision equipment
  • Robotics
  • Fitness/outdoor equipment

Features

  • Powered by NXP i.MX RT application processor
  • Core clock up to 600MHz
  • 512kB on-chip RAM memory
  • 256Mb (32MB) SDRAM memory
  • 128Mb (16MB) QuadSPI Flash memory
  • Power-efficient and cost-optimized solution
  • Ideal for industrial IoT and embedded applications
  • FreeRTOS support

Pictures of SOM versions

Version Photo
RAM&QSPI

Ordering info

SLSNRTCpuType_Clock_RamSize_FlashSize_SF_TEMP
SLSProduct type
SLS - System on Module
NSOM Name
1 - VisionSOM SODIMM200
RTCPU Family
3 - i.MX RT105x/106x
CpuTypeCPU Type
RT1052 - i.MX-RT 1052
ClockCPU Clock Speed
528C - Cortex-M7 @528MHz
RamSizeSDRAM Size
0R - No external SDRAM
16R - 16MB
32R - 32MB
FlashSizeQSPI Flash Size
4QSPI - 4MB QSPI Flash
16QSPI - 16MB QSPI Flash
SFSpecial Features
2ET - 10/100 Ethernet PHY on-board
TEMPOperating Temperature
C - Consumer: 0 to +70 C
I - Industrial: -40 to +85 C

Block Diagram

Operating ranges

Parameter Value Unit Comment
Power Supply
5.0
V
Connected to +5VIN SODIMM pin
Internal LDO output voltage
3.3
V
Generated by internal LDO
Internal LDO output current
500
mA
Maximum value
Input GPIO voltage
0...+3.3
V
-
Environment temperature1
-40…+85
oC Industrial range
0…+70
Consumer range

Note:
1. Maximum MPU junction temperature is +105oC (industrial version) or +95oC (consumer version).

Electrical parameters

SOM
signal name
Parameter Value Units
Min. Typ. Max.
+5VIN Supply Voltage 4.0 5.0 5.5 V
- Total Supply Current1 - 80 150 mA
VGPIO GPIO Input Voltage 0 3.3 3.62 V
+3.3VOUT SOM Internal LDO
Output Current
- - 0.5 A
USB-OTGx-VBUS USB Supply 4.40 - 5.5 V
VDD-COIN-3V SNVS Backup
Battery Supply
2.9 - 3.6 V
- ADC Inputs Voltage 0 - 3.3 V

Notes:
1. Excluding external load connected to +3.3VOUT lines and with Ethernet PHY in stand-by mode.
2. Applying the maximum voltage 3.6V results in shorten lifetime. Recommended value is smaller than 3.5V.

Pinout

Important notes:
1. LCD_DATAxx pins can be used for boot sequence configuration. In such case we recommend to use LCD_DATAxx lines as outputs or using eFuse boot configuration. Currently produced modules are configured using eFuse and LCD_DATAxx pins can be used without restrictions.
2. Internal peripherals and pin functions depends on i.MX-RT version (i.a. in RT1052 there is just one Ethernet channel). Description in table fits to RT1052 MCU.
3. The VisionSOM-RT-ETH module is equipped with hardware system watchdog that is controlled by GPIO_AD_B1_10 line (pin L13).

SOM pin Default function GPIO Ball number Description
(refer to i.MX-RT manuals for details)
1 GND - - -
2 GND - - -
3 PMIC-STBY-REQ - L7 -
4 PWR-POR - - External warm reset (disconnecting PMIC) input, active L.
5 PMIC-ON-REQ - K7 -
6 VDD-SNVS-3V3 - M9 Powered by dedicated on-board LDO 3,3V.
Line powered in parallel by VDD-COIN-3V.
7 BOOT-MODE1 GPIO_AD_B0_05 G14 Internal pull-up 1k
8 VDD-COIN-3V - M9 Optional external coin battery for SNVS power domain, must be held between 2.9V and 3.6V if the system requires keeping real time and other data on OFF state.
Leave open if not used.
Parallel power supply for SNVS domain.
Connected in parallel with the line VDD-SNVS-3V3.
9 BOOT-MODE0 GPIO_AD_B0_04 F11 Internal pull-down 10k.
Multifunction GPIO with 3.3V logic levels.
Pin shared with GPIO-B0-04 line.
10 - - - Not internally connected.
11 USB-OTG2-VBUS - P6 Power supply for USB2 engine.
5V compatible.
12 - - - Not internally connected.
13 USB-OTG1-VBUS - N6 Power supply for USB1 engine.
5V compatible.
14 ONOFF - M6 -
15 GND - - -
16 POR-B - M7 POR_B MCU reset input, active L.
17 GND - - -
18 - - - Not internally connected.
19 USB-OTG2-DP - P7 USB data line.
20 GND - - -
21 USB-OTG2-DN - N7 USB data line.
22 GND - - -
23 GND - - -
24 - - - Not internally connected.
25 USB-OTG1-DP L8 USB data line.
26 GND - - -
27 USB-OTG1-DN M8 USB data line.
28 GND - - -
29 GND - - -
30 - - - Not internally connected.
31 nUSB-OTG-CHD - N12 Refer to i.MX-RT manuals for details.
32 - - - Not internally connected.
33 JTAG-MOD GPIO_AD_B0_08 F13 Internal pull-down 4,7k
34 - - - Not internally connected.
35 GND - - -
36 - - - Not internally connected.
37 CLK1-N - P13 -
38 GND - - -
39 CLK1-P - N13 -
40 GND - - -
41 GND - - -
42 - - - Not internally connected.
43 JTAG-TDI GPIO_AD_B0_09 F14 JTAG TDI input line.
Multifunction GPIO with 3.3V logic levels.
44 - - - Not internally connected.
45 GPIO-B1-09 GPIO_AD_B1_09 M13 Multifunction GPIO with 3.3V logic levels.
46 JTAG-TMS GPIO_AD_B0_06 E14 JTAG TMS input line.
Multifunction GPIO with 3.3V logic levels.
47 GPIO-B0-04 GPIO_AD_B0_04 F11 Internal pull-down 10k.
Multifunction GPIO with 3.3V logic levels.
Pin shared with BOOT-MODE0 line.
48 JTAG-nTRST GPIO_AD_B0_11 G10 JTAG nTRST input line.
Multifunction GPIO with 3.3V logic levels.
49 GPIO-B1-11 GPIO_AD_B1_11 J13 Multifunction GPIO with 3.3V logic levels.
50 GND - - -
51 GND - - -
52 JTAG-TDO GPIO_AD_B0_10 G13 JTAG TDO output line.
Multifunction GPIO with 3.3V logic levels.
53 ENET-MDC GPIO_EMC_40 A7
54 JTAG-TCK GPIO_AD_B0_07 F12 JTAG TCK output line.
Multifunction GPIO with 3.3V logic levels.
55 GPIO-B0-03 GPIO_AD_B0_03 G11 Multifunction GPIO with 3.3V logic levels.
56 GPIO-B1-14 GPIO_B1_14 C14 Multifunction GPIO with 3.3V logic levels.
57 UART1-TXD GPIO_AD_B0_12 K14 UART1 TxD output
or multifunction GPIO with 3.3V logic levels.
58 GPIO-B0-02 GPIO_AD_B0_02 M11 Multifunction GPIO with 3.3V logic levels.
59 GND - - -
60 GND - - -
61 ENET-MDIO GPIO_EMC_41 C7 Multifunction GPIO with 3.3V logic levels.
62 GPIO-B0-01 GPIO_AD_B0_01 H10 Multifunction GPIO with 3.3V logic levels.
63 UART1-RXD GPIO_AD_B0_13 L14 UART2 TxD input
or multifunction GPIO with 3.3V logic levels.
64 GPIO-B0-00 GPIO_AD_B0_00 M14 Multifunction GPIO with 3.3V logic levels.
65 UART2-TXD GPIO_AD_B1_02 L11 UART2 TxD output
or multifunction GPIO with 3.3V logic levels.
66 UART1-CTS GPIO_AD_B0_14 H14 UART1 CTS output
or multifunction GPIO with 3.3V logic levels.
67 UART2-RXD GPIO_AD_B1_03 M12 UART2 RxD input
or multifunction GPIO with 3.3V logic levels.
68 UART5-RXD GPIO_B1_13 D14 UART5 RxD input
or multifunction GPIO with 3.3V logic levels.
69 UART3-TXD GPIO_AD_B1_06 J12 UART3 TxD input
or multifunction GPIO with 3.3V logic levels.
70 GND - - -
71 GND - - -
72 UART2-CTS GPIO_AD_B1_00 J11 UART2 CTS output
or multifunction GPIO with 3.3V logic levels.
73 UART3-RXD GPIO_AD_B1_07 K10 UART3 RxD input
or multifunction GPIO with 3.3V logic levels.
74 UART1-RTS GPIO_AD_B0_15 L10 UART1 RTS input
or multifunction GPIO with 3.3V logic levels.
75 - - - Not internally connected.
76 UART3-CTS GPIO_AD_B1_04 L12 UART3 CTS output
or multifunction GPIO with 3.3V logic levels.
77 - - - Not internally connected.
78 UART2-RTS GPIO_AD_B1_01 K11 UART2 RTS input
or multifunction GPIO with 3.3V logic levels.
79 UART5-TXD GPIO_B1_12 D13 UART5 TxD output
or multifunction GPIO with 3.3V logic levels.
80 UART3-RTS GPIO_AD_B1_05 K12 UART3 RTS input
or multifunction GPIO with 3.3V logic levels.
81 GND - - -
82 GND - - -
83 - - - Not internally connected.
84 GND - - -
85 +3.3VOUT - - +3.3V generated by SOM's LDO.
86 - - - Not internally connected.
87 +3.3VOUT - - +3.3V generated by SOM's LDO.
88 +3.3VOUT - - +3.3V generated by SOM's LDO.
89 +3.3VOUT - - +3.3V generated by SOM's LDO.
90 +3.3VOUT - - +3.3V generated by SOM's LDO.
91 +3.3VOUT - - +3.3V generated by SOM's LDO.
92 +3.3VOUT - - +3.3V generated by SOM's LDO.
93 +3.3VOUT - - +3.3V generated by SOM's LDO.
94 - - - Not internally connected.
95 - - - Not internally connected.
96 +5VIN - - +4.0-5.5V input power supply.
97 ENET1-RXD0 GPIO_B1_04 E12 Signal externally not available as GPIO if Ethernet PHY is mounted on board.
98 +5VIN - - +4.0-5.5V input power supply.
99 ENET1-RXD1 GPIO_B1_05 D12 Signal externally not available as GPIO if Ethernet PHY is mounted on board.
100 +5VIN - - +4.0-5.5V input power supply.
101 ENET1-CRS-DV GPIO_B1_06 C12 Signal externally not available as GPIO if Ethernet PHY is mounted on board.
102 +5VIN - - +4.0-5.5V input power supply.
103 GND - - -
104 +5VIN - - +4.0-5.5V input power supply.
105 - - - Not internally connected.
106 +5VIN - - +4.0-5.5V input power supply.
107 GND - - -
108 +5VIN - - +4.0-5.5V input power supply.
109 - - - Not internally connected.
110 +5VIN - - +4.0-5.5V input power supply.
111 ENET2-RXD0 GPIO_AD_B1_14 G12 Ethernet MAC2-PHY interface signal or multifunction GPIO with 3.3V logic levels.
112 +5VIN - - +4.0-5.5V input power supply.
113 - - - Not internally connected.
114 ENET1-TXEN GPIO_B1_09 A13 Signal externally not available as GPIO if Ethernet PHY is mounted on board.
115 GND - - -
116 GND - - -
117 ENET2-CRS-DV GPIO_AD_B1_15 J14 Ethernet MAC2-PHY interface signal or multifunction GPIO with 3.3V logic levels.
118 ENET1-TX-CLK GPIO_B1_10 B13 Ethernet MAC1-PHY interface signal or multifunction GPIO with 3.3V logic levels.
In series is connected 10R resistor, connected to CLK input of internal PHY.
Signal externally not available as GPIO if Ethernet PHY is mounted on board.
119 ENET2-TXD1 GPIO_AD_B1_13 H11 Ethernet MAC2-PHY interface signal or multifunction GPIO with 3.3V logic levels.
120 GND - - -
121 ENET2-TXEN GPIO_AD_B1_12 H12 Ethernet MAC2-PHY interface signal or multifunction GPIO with 3.3V logic levels.
122 ENET1-TXD0 GPIO_B1_07 B12 Ethernet MAC1-PHY interface signal or multifunction GPIO with 3.3V logic levels.
123 ENET2-TXD0 GPIO_B1_15 B14 Ethernet MAC2-PHY interface signal or multifunction GPIO with 3.3V logic levels.
124 ENET1-TXD1 GPIO_B1_08 A12 Ethernet MAC1-PHY interface signal or multifunction GPIO with 3.3V logic levels.
125 GND - - -
126 ENET1-RXER GPIO_B1_11 C13 Ethernet MAC1-PHY interface signal or multifunction GPIO with 3.3V logic levels.
127 GND - - -
128 GND - - -
129 LCD-DATA21 GPIO_B1_01 B11 LCD interface signal or multifunction GPIO with 3.3V logic levels.
130 GND - - -
131 LCD-DATA22 GPIO_B1_02 C11 LCD interface signal or multifunction GPIO with 3.3V logic levels.
132 GND - - -
133 GND - - -
134 LCD-DATA23 GPIO_B1_03 D11 LCD interface signal or multifunction GPIO with 3.3V logic levels.
135 GND - - -
136 GND - - -
137 GND - - -
138 LCD-DATA19 GPIO_B0_15 E11 LCD interface signal or multifunction GPIO with 3.3V logic levels.
139 LCD-DATA13 GPIO_B0_12 C10 LCD interface signal or multifunction GPIO with 3.3V logic levels.
140 LCD-DATA20 GPIO_B1_00 A11 LCD interface signal or multifunction GPIO with 3.3V logic levels.
141 LCD-DATA14 GPIO_B0_13 D10 LCD interface signal or multifunction GPIO with 3.3V logic levels.
142 LCD-DATA15 GPIO_B0_14 E10 LCD interface signal or multifunction GPIO with 3.3V logic levels.
143 GND - - -
144 GND - - -
145 GND - - -
146 GND - - -
147 GND - - -
148 LCD-DATA11 GPIO_B0_10 D9 LCD interface signal or multifunction GPIO with 3.3V logic levels.
149 LCD-DATA5 GPIO_B0_06 A8 LCD interface signal or multifunction GPIO with 3.3V logic levels.
150 LCD-DATA12 GPIO_B0_11 A10 LCD interface signal or multifunction GPIO with 3.3V logic levels.
151 LCD-DATA6 GPIO_B0_07 A9 LCD interface signal or multifunction GPIO with 3.3V logic levels.
152 LCD-DATA10 GPIO_B0_09 C9 LCD interface signal or multifunction GPIO with 3.3V logic levels.
153 GND - - -
154 LCD-DATA3 GPIO_B0_04 C8 LCD interface signal or multifunction GPIO with 3.3V logic levels.
155 GND - - -
156 GND - - -
157 LCD-RESET GPIO_AD_B1_08 H13 LCD interface signal or multifunction GPIO with 3.3V logic levels.
158 LCD-DATA4 GPIO_B0_05 B8 LCD interface signal or multifunction GPIO with 3.3V logic levels.
159 GND - - -
160 LCD-HSYNC GPIO_B0_02 E8 LCD interface signal or multifunction GPIO with 3.3V logic levels.
161 LCD-CLK GPIO_B0_00 D7 LCD interface signal or multifunction GPIO with 3.3V logic levels.
162 LCD-VSYNC GPIO_B0_03 D8 LCD interface signal or multifunction GPIO with 3.3V logic levels.
163 LCD-ENABLE GPIO_B0_01 E7 LCD interface signal or multifunction GPIO with 3.3V logic levels.
164 GND - - -
165 GND - - -
166 LCD-DATA7 GPIO_B0_08 B9 LCD interface signal or multifunction GPIO with 3.3V logic levels.
167 SDIO1-D0 GPIO_SD_B0_02 J4 SDIO interface signal or multifunction GPIO with 3.3V logic levels.
168 - - - Not internally connected.
169 SDIO1-D3 GPIO_SD_B0_05 J2 SDIO interface signal or multifunction GPIO with 3.3V logic levels.
170 - - - Not internally connected.
171 SDIO1-D1 GPIO_SD_B0_03 K1 SDIO interface signal or multifunction GPIO with 3.3V logic levels.
172 - - - Not internally connected.
173 SDIO1-CMD GPIO_SD_B0_00 J4 SDIO interface signal or multifunction GPIO with 3.3V logic levels.
174 - - - Not internally connected.
175 SDIO1-D2 GPIO_SD_B0_04 H2 SDIO interface signal or multifunction GPIO with 3.3V logic levels.
176 - - - Not internally connected.
177 GND - - -
178 - - - Not internally connected.
179 SDIO1-CLK GPIO_SD_B0_01 J3
180 - - - Not internally connected.
181 GND - - -
182 - - - Not internally connected.
183 ENET-LED0 LED0/nWAYEN (KSZ8081RNBCA) - 220R resistor connected in series
1k pull-down resistor
184 GND - - -
185 GND - - -
186 - - - Not internally connected.
187 ENET-LED1 LED1/SPEED (KSZ8081RNBCA) - 220R resistor connected in series
1k pull-down resistor
188 - - - Not internally connected.
189 GND - - -
190 - - - Not internally connected.
191 ENET-RXN RXN (KSZ8081RNBCA) - RX- PHY input (external transformer)
192 - - - Not internally connected.
193 ENET-RXP RXP (KSZ8081RNBCA) - RX+ PHY input (external transformer)
194 - - - Not internally connected.
195 ENET-TXN TXN (KSZ8081RNBCA) - TX- PHY output (external transformer)
196 - - - Not internally connected.
197 ENET-TXP TXP (KSZ8081RNBCA) - TX+ PHY output (external transformer)
198 - - - Not internally connected.
199 GND - - -
200 GND - - -

On-board Ethernet PHY configuration

Important notes:
1. VisionSOM-RT-ETH is equipped with KSZ8081RNBCA Ethernet PHY chip.
2. MDC and MDIO lines are not used for PHY configuration.
3. Hardware interrupt (line INTRP/NAND_TREE of PHY) is not connected to MCU.
4. The clock signal for Ethernet PHY (line ENET1.TX-CLK) is generated on GPIO_B1_10 (ball B13) of MCU.

PHY configuration pin no PHY configuration pin name Note
16 RXD0/DUPLEX 1k pull-down
15 RXD1/PHYAD2 1k pull-down
14 PHYAD1 1k pull-down
13 PHYAD0 4,7k pull-up
18 CRS_DV/CONFIG2 1k pull-down
20 RXER/ISO 1k pull-down
28 CONFIG0 4,7k pull-up
29 CONFIG1 1k pull-down
30 LED0/nWAYEN 1k pull-down
31 LED1/SPEED 1k pull-down

On-board JTAG connector

The VisionSOM-RT-ETH is equipped with on-board JTAG connector.

J600 connector pin JTAG signal SOM pin
1 VDD-3V3 85
2 JTAG-TMS 46
3 JTAG-TCK 54
4 JTAG-TDO 52
5 JTAG-TDI 43
6 JTAG-nTRST 48
7 POR-B 16
8 GND 28

Dimensions