Customizing the device tree

GPIO pins definitions

Each pin definition in the dts file has three parts. First is the physical pad name (for example MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0), second one is selected pin function (for example MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0). All possible combinations are defined in kernel sources: arch/arm/boot/dts/imx6ul-pinfunc.h. The third part (for example MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0) can be used to perform additional pin configuration, its bits are defined as follows (kernel docummentation: Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt):

PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (0 << 6)
PAD_CTL_SPEED_MED               (1 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_260ohm              (1 << 3)
PAD_CTL_DSE_130ohm              (2 << 3)
PAD_CTL_DSE_87ohm               (3 << 3)
PAD_CTL_DSE_65ohm               (4 << 3)
PAD_CTL_DSE_52ohm               (5 << 3)
PAD_CTL_DSE_43ohm               (6 << 3)
PAD_CTL_DSE_37ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)

You can also use 0x80000000 value, then default pin configuration will be used.

GPIO Input

In this example the following pins are configured as inputs:

GPIO1_IO08 (45 pin of the VisionSOM-6ULx module)
GPIO1_IO09 (56 pin of the VisionSOM-6ULx module)

These pins are connected to the IO8 and IO9 buttons on the VisionCB-STB board.

Both pins need to be configured in the device tree file. In this example a new section of the visioncb-6ull entry in the visioncb-6ull-std.dtsi file is created:

pinctrl_gpio_in: gpioingrp {
	fsl,pins = < 
		MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b0b0 
		MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b0b0 
	>; 
};

This definition needs to be also linked to the iomux entry:

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_gpio_in>;

Now, both inputs may be used by exporting the pins:

echo 8 > /sys/class/gpio/export
echo 9 > /sys/class/gpio/export

setting them as inputs:

echo in > /sys/class/gpio/gpio8/direction
echo in > /sys/class/gpio/gpio9/direction

and reading the input value:

cat /sys/class/gpio/gpio8/value
cat /sys/class/gpio/gpio9/value

I2C

Adding a new I2C interface requires defining a new section in the dts file:

&i2c2 {
        clock_frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
};

Second step is the definition of the new pins in the iomux section (pinctrl_i2c2):

&iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog_1>;
        visioncb-6ull {
  
                ...
                ...

                pinctrl_i2c2: i2c2grp {
                        fsl,pins = <
                                MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
                                MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
                        >;
                }
                
                ...
                ...
                
};

UART

In this example the UART4 port is added with the following signals: UART4 RX (77 pin of the VisionSOM-6ULx module) UART4 TX (75 pin of the VisionSOM-6ULx module) The new pins need to be defined in the visioncb-6ull section of the iomux configuration (visioncb-6ull-std.dtsi file):

pinctrl_uart4: uart4grp {
	fsl,pins = < 
		MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
		MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
	>; 
};

After that, the new port may be added as a new section in the device tree file:

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay"; 
};

After system boot, the new port will be visible as the /dev/ttymxc3 file.

Building device tree

After finishing the customization of the device tree it can be built from the main kernel directory by calling:

make ARCH=arm CROSS_COMPILE=<compiler_path> dtbs

The CROSS_COMPILE environmental variable should be set according to the cross compiler installation path.

The are compiled device tree blob files:

visioncb-6ull-std-emmc-btwifi.dtb
visioncb-6ull-std-emmc.dtb
visioncb-6ull-std-sd-btwifi.dtb
visioncb-6ull-std-sd.dtb

Installing new device tree files

The new device tree file should be copied to the target system and by replacing existing one. In case of SoMLabs Debian the recognized names are:

visionsom-6ull.dtb - for SD card module
visionsom-6ull-emmc.dtb - for eMMC module

The original files are located on the boot partition that should be mounted by using the following command:

mount /dev/mmcblk1p1 /boot

NOTE! It is strongly recommended to check startup messages after loading the device tree. If one of I/O lines is requested by more than one driver then you will get message like the one below:

[    0.322774] imx6ul-pinctrl 20e0000.iomuxc: pin MX6UL_PAD_JTAG_TCK already requested by 20e0000.iomuxc; cannot claim for 20f4000.pwm
[    0.322821] imx6ul-pinctrl 20e0000.iomuxc: pin-21 (20f4000.pwm) status -22
[    0.322859] imx6ul-pinctrl 20e0000.iomuxc: could not request pin 21 (MX6UL_PAD_JTAG_TCK) from group pwm6grp  on device 20e0000.iomuxc

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