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[[File:SL-ADP-PCIe-M2-ssd.png|800px|center]]
 
[[File:SL-ADP-PCIe-M2-ssd.png|800px|center]]
 
<br>  
 
<br>  
−
SL-ADP-PCIe-M2 is adapter dedicated to using M.2 mass storage (SSD) in embedded systems based on i.MX8Mmini.
+
SL-ADP-PCIe-M2 is adapter dedicated to using M.2 mass storage (SSD, single lane) in embedded systems based on i.MX8Mmini MPU. The SL-ADP-PCIe-M2 module is equipped with M.2 key M connector and is compatible with 2242, 2260 or 2280 modules.<br>The SL-ADP-PCIe-M2 module is equipped with FPC16 connector - the same like in SoMLabs carrier board VisionCB-8M-STD.
−
The SL-ADP-PCIe-M2 module is equipped with FPC16 connector - the same like in SoMLabs carrier board VisionCB-8M-STD.
 
  
 
== Features ==
 
== Features ==
 
* Equipped with M.2 key M SSD socket
 
* Equipped with M.2 key M SSD socket
 
* Single rail +3.3V power supply
 
* Single rail +3.3V power supply
−
* SSD configuration via I2C
+
* Single lane PCIe communication interface
 
* Operating temperature -30÷+85°C
 
* Operating temperature -30÷+85°C
 
* Fully compatible with SoMLabs carrier boards equippped with PCIe interface on FPC16 connector
 
* Fully compatible with SoMLabs carrier boards equippped with PCIe interface on FPC16 connector
Line 19: Line 18:
  
 
== Pictures ==
 
== Pictures ==
−
[[File:SL-MIPI-CSI-OV5640-2.jpg|800px|center]]<br>
+
Note: the SSD module shown in the picture is not included in the SL-ADP-PCIe-M2 kit!
−
[[File:SL-MIPI-CSI-OV5640-3.jpg|800px|center]]<br>
+
 
−
[[File:SL-MIPI-CSI-OV5640-4.jpg|800px|center]]<br>
+
[[File:SL-ADP-PCIe-M2-2.jpg|800px|center]]<br>
−
[[File:SL-MIPI-CSI-OV5640-5.jpg|800px|center]]<br>
+
[[File:SL-ADP-PCIe-M2-3.jpg|800px|center]]<br>
 +
[[File:SL-ADP-PCIe-M2-4.jpg|800px|center]]<br>
 +
[[File:SL-ADP-PCIe-M2-5.jpg|800px|center]]<br>
  
 
== Ordering info ==
 
== Ordering info ==
−
'''SL-MIPI-CSI-OV5640''' - FPC 30-pin flat cable (A-A) is included.
+
'''SL-ADP-PCIe-M2''' - FPC 16-pin flat cable (A-A) is included. The SSD module is not included in the SL-ADP-PCIe-M2 kit.
  
 
== Operating ranges ==
 
== Operating ranges ==
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|-
 
|-
 
| Current
 
| Current
−
| <center>0.16</center>
+
| <center>15</center>
−
| <center>A</center>
+
| <center>mA</center>
−
| Maximum peak value
+
| Maximum peak value (excluding SSD module)
 
|-  
 
|-  
 
|Working temperature
 
|Working temperature
−
|<center>-30…+70</center>
+
|<center>-30…+85</center>
 
|<sup>o</sup>C
 
|<sup>o</sup>C
 
| -
 
| -
Line 70: Line 71:
 
| I<sub>3.3V</sub>
 
| I<sub>3.3V</sub>
 
| Supply Current (3.3V)
 
| Supply Current (3.3V)
−
| 0.11
+
| 1
−
| .16
 
 
| -
 
| -
 +
| 15
 
| mA
 
| mA
 
|-
 
|-
−
| t<sub>PWRSEQ</sub>
+
| f<sub>SUSCLK</sub>
−
| PMIC power-up time
+
| Suspend mode CLK frequency
−
| -
 
−
| 150
 
−
| -
 
−
| ms
 
−
 
 
−
|-
 
−
| VIO
 
−
| I2C, RES, PWDN Input Voltage
 
−
| 0
 
−
| 3.3
 
−
| 3.5
 
−
| V
 
−
|-
 
−
| f<sub>I2C</sub>
 
−
| I2C Controller Speed
 
 
| -
 
| -
 +
| 32
 
| -
 
| -
−
| 400
 
 
| kHz
 
| kHz
 
|-
 
|-
−
| R<sub>I2C</sub>
 
−
| I2C IOs Pull-up Resistance
 
−
| -
 
−
| 10
 
−
| -
 
−
| kΩ
 
−
|-
 
−
| R<sub>PWDN</sub>
 
−
| Serial resistors voltage divider connected between FPC30 pin and PWDN input of OV5640 sensor
 
−
| -
 
−
| 2x10
 
−
| -
 
−
| kΩ
 
 
|}
 
|}
 +
<br>Note:
 +
<br>1. Current consumption value without SSD module.
  
−
== MIPI-CSI (output) Pinout ==
+
== PCIe Pinout ==
 
<br>
 
<br>
−
[[File:SL-MIPI-CSI-OV5640-conn.png|center]]
+
[[File:SL-ADP-PCIe-M2-conn.jpg|center]]
 
<br />
 
<br />
 
<br>
 
<br>
 
{| class="wikitable"
 
{| class="wikitable"
−
! style="text-align: center; font-weight: bold;" | FPC30 connector pin
+
! style="text-align: center; font-weight: bold;" | FPC16 connector pin
 
! style="text-align: center; font-weight: bold;" | Function name
 
! style="text-align: center; font-weight: bold;" | Function name
 
! style="text-align: center; font-weight: bold;" | Description
 
! style="text-align: center; font-weight: bold;" | Description
 
|-
 
|-
 
| 1
 
| 1
−
| GND
+
| -
 
| -
 
| -
 
|-
 
|-
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|-
 
|-
 
| 3
 
| 3
−
| -
+
| +3.3V
−
| -
+
| Power supply
 
|-
 
|-
 
| 4
 
| 4
−
| -
+
| +3.3V
−
| -
+
| Power supply
 
|-
 
|-
 
| 5
 
| 5
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|-
 
|-
 
| 6
 
| 6
−
| +3.3V
+
| -
−
| Power supply
+
| -
 
|-
 
|-
 
| 7
 
| 7
−
| +3.3V
+
| GND
−
| Power supply
+
| -
 
|-
 
|-
 
| 8
 
| 8
−
| GND
+
| PCIe_CLK_n
−
| -
+
| Negative CLK data lane
 
|-
 
|-
 
| 9
 
| 9
−
| -
+
| PCIe_CLK_p
−
| -
+
| Positive CLK data lane
 
|-
 
|-
 
| 10
 
| 10
−
| PWDN
+
| GND
−
| OV5640 - Power Down input (active high, internal pull-down)
+
| -
 
|-
 
|-
 
| 11
 
| 11
−
| RESET
+
| PCIe_TXN_p
−
| OV5640 - Reset input (active low, internal pull-up)
+
| Positive TX data lane
 
|-
 
|-
 
| 12
 
| 12
 +
| PCIe_TXN_n
 +
| Negative TX data lane
 +
|-
 +
| 13
 
| GND
 
| GND
 
| -
 
| -
−
|-
 
−
| 13
 
−
| SIOD_C
 
−
| SDA line of configuration I2C interface (internal pull-up)
 
 
|-
 
|-
 
| 14
 
| 14
−
| SIO_D
+
| PCIe_RXN_p
−
| SCL line of configuration I2C interface (internal pull-up)
+
| Positive RX data lane
 
|-
 
|-
 
| 15
 
| 15
−
| GND
+
| PCIe_RXN_n
−
| -
+
| Negative RX data lane
 
|-
 
|-
 
| 16
 
| 16
−
| -
 
−
| -
 
−
|-
 
−
| 17
 
−
| -
 
−
| -
 
−
|-
 
−
| 18
 
−
| GND
 
−
| -
 
−
|-
 
−
| 19
 
−
| -
 
−
| -
 
−
|-
 
−
| 20
 
−
| -
 
−
| -
 
−
|-
 
−
| 21
 
−
| GND
 
−
| -
 
−
|-
 
−
| 22
 
−
| MDN1
 
−
| CSI_DATA1_n
 
−
|-
 
−
| 23
 
−
| MDP1
 
−
| CSI_DATA1_p
 
−
|-
 
−
| 24
 
−
| GND
 
−
| -
 
−
|-
 
−
| 25
 
−
| MDN0
 
−
| CSI_DATA0_n
 
−
|-
 
−
| 26
 
−
| MDP0
 
−
| CSI_DATA0_p
 
−
|-
 
−
| 27
 
−
| GND
 
−
| -
 
−
|-
 
−
| 28
 
−
| MCN
 
−
| CSI_CLK_n
 
−
|-
 
−
| 29
 
−
| MCP
 
−
| CSI_CLK_p
 
−
|-
 
−
| 30
 
 
| GND
 
| GND
 
| -
 
| -
 
|-
 
|-
 
|}
 
|}
 +
<br>Note:
 +
<br>1. nPERST, nCLKREQ and nPEWAKE pins are connected to +3.3V with 10k pull-up resistors.
 +
<br>2. 32kHz generator connected to SUSCLK input.
 +
<br>3. ACT LED is controlled by DAS/DSS/nLED1 pin.
  
 
== Dimensions ==
 
== Dimensions ==
 
<br>
 
<br>
−
[[File:SL-MIPI-CSI-OV5640-dimension.png|center]]
+
[[File:SL-ADP-PCIe-M2-dimension.jpg|center]]

Latest revision as of 13:28, 4 May 2021

SL-ADP-PCIe-M2 M.2 PCIe mass storage adapter Datasheet and Pinout

General description

SL-ADP-PCIe-M2-ssd.png


SL-ADP-PCIe-M2 is adapter dedicated to using M.2 mass storage (SSD, single lane) in embedded systems based on i.MX8Mmini MPU. The SL-ADP-PCIe-M2 module is equipped with M.2 key M connector and is compatible with 2242, 2260 or 2280 modules.
The SL-ADP-PCIe-M2 module is equipped with FPC16 connector - the same like in SoMLabs carrier board VisionCB-8M-STD.

Features

  • Equipped with M.2 key M SSD socket
  • Single rail +3.3V power supply
  • Single lane PCIe communication interface
  • Operating temperature -30÷+85°C
  • Fully compatible with SoMLabs carrier boards equippped with PCIe interface on FPC16 connector
  • Built-in 32kHz clock source
  • Built-in two LEDs
  • Compatible with 2242, 2260 and 2280 modules
  • Connection with carrier board using FPC16 cable

Pictures

Note: the SSD module shown in the picture is not included in the SL-ADP-PCIe-M2 kit!

SL-ADP-PCIe-M2-2.jpg

SL-ADP-PCIe-M2-3.jpg

SL-ADP-PCIe-M2-4.jpg

SL-ADP-PCIe-M2-5.jpg

Ordering info

SL-ADP-PCIe-M2 - FPC 16-pin flat cable (A-A) is included. The SSD module is not included in the SL-ADP-PCIe-M2 kit.

Operating ranges

Parameter Value Unit Comment
Power Supply
3.3
V
 Powered from carrier board
Current
15
mA
 Maximum peak value (excluding SSD module)
Working temperature
-30…+85
 oC -

Electrical parameters

Signal name Parameter Value Units
Min. Typ. Max.
+3.3V Supply Voltage 3.2 3.3 3.35 V
I3.3V Supply Current (3.3V) 1 - 15 mA
fSUSCLK Suspend mode CLK frequency - 32 - kHz


Note:
1. Current consumption value without SSD module.

PCIe Pinout


SL-ADP-PCIe-M2-conn.jpg



FPC16 connector pin Function name Description
1 - -
2 - -
3 +3.3V Power supply
4 +3.3V Power supply
5 - -
6 - -
7 GND -
8 PCIe_CLK_n Negative CLK data lane
9 PCIe_CLK_p Positive CLK data lane
10 GND -
11 PCIe_TXN_p Positive TX data lane
12 PCIe_TXN_n Negative TX data lane
13 GND -
14 PCIe_RXN_p Positive RX data lane
15 PCIe_RXN_n Negative RX data lane
16 GND -


Note:
1. nPERST, nCLKREQ and nPEWAKE pins are connected to +3.3V with 10k pull-up resistors.
2. 32kHz generator connected to SUSCLK input.
3. ACT LED is controlled by DAS/DSS/nLED1 pin.

Dimensions


SL-ADP-PCIe-M2-dimension.jpg
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